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F71862 参数 Datasheet PDF下载

F71862图片预览
型号: F71862
PDF下载: 下载PDF文件 查看货源
内容描述: 超级硬件监控+ LPC I / O [Super Hardware Monitor + LPC I/O]
分类和应用: 监控PC
文件页数/大小: 110 页 / 837 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71862  
1-0 DRATE  
W
10  
These bit determine the data rate of the floppy controller. See DRATE bits in  
Data Rate Select Register.  
FDC Commands  
Terminology:  
C
Cylinder Number 0 -256  
Data Pattern  
Step Direction  
0: step out  
1: step in  
D
DIR  
DS0  
DS1  
DTL  
EC  
EOT  
EFIFO  
Drive Select 0  
Drive Select 1  
Data Length  
Enable Count  
End of Track  
Enable FIFO  
0: FIFO is enabled.  
1: FIFO is disabled.  
Enable Implied Seek  
EIS  
FIFOTHR FIFO Threshold  
GAP  
GPL  
H/HDS  
HLT  
HUT  
LOCK  
Alters Gap Length  
Gap Length  
Head Address  
Head Load Time  
Head Unload Time  
Lock EFIFO, FIFOTHR, PTRTRK bits.  
Prevent these bits from being affected by software reset.  
MFM  
MFM or FM mode  
0: FM  
1: MFM  
MT  
N
Multi-Track  
Sector Size Code. All values up to 07h are allowable.  
00:  
01:  
..  
128 bytes  
256 bytes  
..  
07  
16 Kbytes  
NCN  
ND  
OW  
New Cylinder Number  
Non-DMA Mode  
Overwritten  
PCN  
POLL  
Present Cylinder Number  
Polling disable  
0: polling is enabled.  
1: polling is disabled.  
PRETRK Precompensation Start Track Number  
R
RCN  
SC  
SK  
SRT  
ST0  
ST1  
ST2  
ST3  
WGATE  
Sector address  
Relative Cylinder Number  
Sector per Cylinder  
Skip deleted data address mark  
Step Rate Time  
Status Register 0  
Status Register 1  
Status Register 2  
Status Register 3  
Write Gate alters timing of WE.  
25  
July, 2008  
V.28P  
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