F71869A
6.6.11 Configuration Register ⎯ Index 0Ah
Bit
Name
R/W Default
Description
0: disable the T1 beta compensation.
1: enable the T1 beta compensation.
0: AMD model.
7
BETA_EN
R/W
0
1
6
INTEL_MODEL R/W
1: Intel model.
5
4
Reserved
-
0
0
Reserved.
Reserved
MXM_MODE
R/W
PECI (Vtt) voltage select.
00: Vtt is 1.23V
3-2
VTT_SEL
R/W
0
01: Vtt is 1.13V
10: Vtt is 1.00V
11: Vtt is 1.00V
0: Disable the TSI function via PECI / CIR_LED / PCI_RST4# /
PCI_RST5# pins.
1: Enable the TSI function via PECI / CIR_LED / PCI_RST4# /
PCI_RST5# pins.
This bit accompanies with INTEL_MODEL, IBX_ALT_EN, PECI_EN,
and it determines the availability of AMD TSI, Intel PCH SMBus, or
PECI.
Setting (CR07[0]-- NEW_TSI_MODE = 0)
INTEL TSI_
PECI_
EN
(CR0A, (CR2A, bit6
IBX_ALT_
EN
PE AMD
Intel
PCH
SMBus
_MOD
EL
(CR0
A,
EN
CI
TSI
(CR0
bit0)
in global
configurati
on register)
A,
bit6)
bit1)
0
0
1
1
1
0
1
0
1
1
X
X
1
1
0
X
X
X
1
N
N
Y
Y
N
N
Y
N
N
N
N
N
N
Y
Y
1
TSI_EN
R/W
0
X
Setting (CR07[0]-- NEW_TSI_MODE = 1)
INTEL TSI_
PECI_
EN
IBX_ALT_
EN
PE AMD
Intel
PCH
_MOD
EN
CI
TSI
EL
(CR0
A,
(CR0 (CR0A, (CR2A, bit6
SMBus
A,
bit0)
in global
bit1)
configurati
bit6)
0
0
1
1
on register)
0
1
0
1
1
X
X
1
1
0
X
X
X
1
N
N
Y
Y
N
N
N
N
Y
Y
N
Y
N
N
N
1
X
0: Disable PECI function via PECI pin
1: Enable PECI function via PECI pin
0
PECI_EN
R/W
0
73
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
