F71869A
30
60
61
70
GPIO Device Enable Register
Base Address High Register
Base Address Low Register
GPIRQ Channel Select Register
-
0
0
-
-
0
0
-
-
0
0
-
-
0
0
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
F0
F1
F2
F3
E0
E1
E2
E3
E4
E5
E6
D0
D1
D2
D3
C0
C1
C2
B0
B1
B2
B3
B4
B5
B6
A0
A1
A2
A4
A5
A6
A9
AB
GPIO Output Enable Register
GPIO Output Data Register
-
-
-
-
0
1
-
0
1
-
0
1
-
0
1
-
0
1
-
0
1
-
GPIO Pin Status Register
-
-
GPIO Drive Enable Register
GPIO1 Output Enable Register
GPIO1 Output Data Register
GPIO1 Pin Status Register
-
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
1
-
0
1
-
GPIO1 Drive Enable Register
GPIO1 PME Enable Register
GPIO1 Detect Edge Select Register
GPIO1 PME Status Register
GPIO2 Output Enable Register
GPIO2 Output Data Register
GPIO2 Pin Status Register
0
0
0
0
0
1
-
0
0
0
0
0
1
-
0
0
0
0
0
1
-
0
0
0
0
0
1
-
0
0
0
0
0
1
-
0
0
0
0
0
1
-
0
0
0
0
0
1
-
0
0
0
0
0
1
-
GPIO2 Drive Enable Register
GPIO3 Output Enable Register
GPIO3 Output Data Register
GPIO3 Pin Status Register
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
GPIO4 Output Enable Register
GPIO4 Output Data Register
GPIO4 Pin Status Register
-
-
-
-
0
1
-
0
1
-
0
1
-
0
1
-
-
-
-
-
-
-
-
-
GPIO4 Drive Enable Register
GPIO4 PME Enable Register
GPIO4 Detect Edge Select Register
GPIO4 PME Status Register
GPIO5 Output Enable Register
GPIO5 Output Data Register
GPIO5 Pin Status Register
-
-
-
-
0
0
0
0
0
1
-
0
0
0
0
0
1
-
0
0
0
0
0
1
-
0
0
0
0
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
1
-
-
-
-
-
-
-
GPIO5 PME Enable Register
GPIO5 Detect Edge Select Register
GPIO5 PME Status Register
GPIO5 KBC Emulation Control Register 1
GPIO5 KBC Emulation Make Code Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
52
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
