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MC81F4432Q 参数 Datasheet PDF下载

MC81F4432Q图片预览
型号: MC81F4432Q
PDF下载: 下载PDF文件 查看货源
内容描述: ABOV半导体的8位单芯片微控制器产品 [ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS]
分类和应用: 半导体微控制器
文件页数/大小: 198 页 / 4293 K
品牌: FINECHIPS [ FINECHIPS ]
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MC81F4432  
25.3 Message format  
Figure 25-2 Data transfer on the IIC-BUS  
START, Repeated START and STOP  
One IIC data message is started by START conditionand finished by STOPor STARTcondition.  
If one message is finished by STARTcondition, it means both an end of the current message and a  
start of the next message at the same time. So we call it repeated START condition.  
Repeated START is used to keep the IIC communication bus. If master transmit the STOP condition,  
other masters can take the bus. To prevent it, the repeated START condition is used.  
When SDA(data line) is changed while SCL(clock line) is staying high, it must be one of START,  
repeated Start or STOP condition. In other words, changing SDA state while SCL is staying high is  
not possible except those conditions.  
START : SDA is changed from HIGH to LOW while SCL is staying high.  
STOP : SDA is changed from LOW to HIGH while SCL is staying high.  
Repeated START : START condition at the end of the frame.  
Message Transmit  
After START or repeated START condition, one byte data is transferred from master to slave. The first  
one byte data consist of 7 bit address and 1 bit read/write flag.  
And 1 bit ACK(acknowledge) is transferred from slave to master to notice that receiving process is  
correctly finished and the slave address is matched.  
Note: Simply transmitting 0is ACK.  
After then, one or more data bytes are transferred. The data bytes are sent MSB first.  
It is possible both master to slave and slave to master based on the read/write bit flag (the last bit of  
the first one byte).  
Write = read/write bit is 0 = data is transferred from master to slave.  
October 19, 2009 Ver.1.35  
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