MC81F4432
IICSCR
SLAVE IIC STATUS AND CONTROL REGISTER
00E2H
7
6
5
4
3
2
1
0
ACKE IICEN IICIFEN IICAZS IICTR
R/W R/W R/W R/W
IICBS
SAM
IICLR
IICSCR
Reset value: 00H
R
R
R
R
0: Disable ACK generation
1: Enable ACK generation
0: Disable IIC-Bus module
1: Enable IIC-Bus module
ACKE
IICEN
IIC-Bus Acknowledgement Enable Bit
IIC-Bus Module Enable Bit
0: IICIF (interrupt flag) cannot be
generated and IIC interrupt is disabled.
IICIFEN
IICAZS
IICTR
IICBS
SAM
IICIF Enable/Disable Bit
1: IICIF (interrupt flag) can be generated
and IIC interrupt is also enabled.
0: It is cleared when start or stop
condition is generated.
IIC-Bus Address Zero Status Flag
Slave IIC-Bus Tx/Rx mode Status Bit
IIC-Bus Busy Status Bit
1: It is set when received slave address
is 00H (general call)
It is set or cleared by W/R signal from
the master.
0: Slave Receive mode
1: Slave transmit mode
0: IIC-bus is not busy (It is cleared when
„stop‟ condition is received).
1: IIC-bus is busy (It is set when „start‟
condition is received).
0: It is cleared when start or stop or
reset condition is generation
Slave Address Match Bit
1: When received slave address value
matches to „SIAR‟ register
0: Last-received 9th bit is “0” (ACK was
received)
IICLR
IIC-Bus Last Received Bit Status Bit
1: Last-received 9th bit is “1” (ACK was
not received)
Note : The IICIFEN must be set by „1‟ to use IIC interrupt. If it is cleared by „0‟ IIC interrupt is
not occurred.
So, in order to use IIC interrupt, both IICIFEN(IICSCR.5) and IICEN(IENL.7) must be set by
„1‟.
October 19, 2009 Ver.1.35
161
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