MC81F4432
Setup Procedure for Multiprocessor Communications
Follow these steps to configure multiprocessor communications:
1. Set all MC81F4x32 devices (masters and slaves) to UART mode 2 or 3.
2. Write the MCE bit of all the slave devices to "1".
3. The master device's transmission protocol is:
- First byte: the address identifying the target slave device (9th bit = "1")
- Next bytes: data (9th bit = "0")
4. When the target slave receives the first byte, all of the slaves are interrupted because the 9th
data bit is "1". The targeted slave compares the address byte to its own address and then
clears its MCE bit in order to receive incoming data. The other slaves continue operating
normally.
24.5 Interrupt
Interrupt Timing
In mode 0, the URIR(IRQL.4) bit is set to "1" when the 8th receive data bit has been shifted. In mode
1, the URIR(IRQL.4) bit is set to "1" at the halfway point of the stop bit's shift time.
In mode 2, or 3, the URIR(IRQL.4) bit is set to "1" at the halfway point of the RB8 bit's shift time.
When the CPU has acknowledged the receive interrupt request flag condition, the URIR(IRQL.4) bit is
automatically cleared.
In mode 0, the UTIR(IRQL.3) bit is set to "1" when the 8th transmit data bit has been shifted. In mode
1, 2, or 3, the UTIR(IRQL.3) bit is set at the start of the stop bit. When the CPU has acknowledged the
transmit interrupt request flag condition, the UTIR(IRQL.3) 4 bit is automatically cleared.
Shared Interrupt Vector
In case of using interrupts of UART Tx and UART Rx together, it is necessary to check UTIF and
URIF in interrupt service routine to find out which interrupt is occurred, because the UART Tx and
UART Rx is shared with the same interrupt vector address. These flag bits must be cleared by
software after reading this register. ( UTIF and URIF are placed in INTFL register. See „9.6 Control
Registers ( SFR )‟ on page 56)
October 19, 2009 Ver.1.35
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