FM25Q64ꢀ
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11.1.6ꢀStatusꢀRegisterꢀprotectꢀ(SRP1,ꢀSRP0)ꢀ
TheꢀStatusꢀRegisterꢀProtectꢀbitsꢀ(SRP1ꢀandꢀSRP0)ꢀareꢀnonꢁvolatileꢀread/writeꢀbitsꢀinꢀtheꢀstatusꢀ
registerꢀ (S8ꢀ andꢀ S7).ꢀ Theꢀ SRPꢀ bitsꢀ controlꢀ theꢀ methodꢀ ofꢀ writeꢀ protection:ꢀ softwareꢀ protection,ꢀ
hardwareꢀprotection,ꢀpowerꢀsupplyꢀlockꢁdownꢀorꢀoneꢀtimeꢀprogrammableꢀ(OTP)ꢀprotection.ꢀ
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Statusꢀ ꢀ
Registerꢀ
SRP1ꢀ SRP0ꢀ
/WPꢀ
Descriptionꢀ
Softwareꢀ
Protectionꢀ
/WPꢀpinꢀnoꢀcontrol.ꢀTheꢀregisterꢀcanꢀbeꢀwrittenꢀtoꢀ
afterꢀaꢀWriteꢀEnableꢀinstruction,ꢀWEL=1.ꢀ[FactoryꢀDefault]ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
Xꢀ
Hardwareꢀ
Protectedꢀ
Whenꢀ/WPꢀpinꢀisꢀlowꢀtheꢀStatusꢀRegisterꢀlockedꢀandꢀcanꢀnotꢀ
beꢀwrittenꢀto.ꢀ
0ꢀ
1ꢀ
Xꢀ
Xꢀ
Hardwareꢀ
Unprotectedꢀ
Whenꢀ /WPꢀ pinꢀ isꢀ highꢀ theꢀ Statusꢀ registerꢀ isꢀ unlockedꢀ andꢀ
canꢀbeꢀwrittenꢀtoꢀafterꢀaꢀWriteꢀEnableꢀinstruction,ꢀWEL=1ꢀ
StatusꢀRegisterꢀisꢀprotectedꢀandꢀcanꢀnotꢀbeꢀwrittenꢀtoꢀagainꢀ
untilꢀtheꢀnextꢀpowerꢁdown,ꢀpowerꢁupꢀcycle(1).ꢀ
PowerꢀSupplyꢀ
LockꢁDownꢀ
OneꢀTimeꢀ
Programꢀ
Statusꢀ Registerꢀ isꢀ permanentlyꢀ protectedꢀ andꢀ canꢀ notꢀ beꢀ
writtenꢀto.ꢀ
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ꢀ Note:ꢀ
1.ꢀWhenꢀSRP1,ꢀSRP0=(1,0),ꢀaꢀpowerꢁdown,ꢀpowerꢁupꢀcycleꢀwillꢀchangeꢀSRP1,ꢀSRP0ꢀto(0,0)ꢀstate.ꢀ
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11.1.7ꢀErase/ProgramꢀSuspendꢀStatusꢀ(SUS)ꢀ ꢀ
TheꢀSuspendꢀStatusꢀbitꢀisꢀaꢀreadꢀonlyꢀbitꢀinꢀtheꢀstatusꢀregisterꢀ(S15)ꢀthatꢀisꢀsetꢀtoꢀ1ꢀafterꢀexecutingꢀ
anꢀErase/ProgramꢀSuspendꢀ(75h)ꢀinstruction.ꢀTheꢀSUSꢀstatusꢀbitꢀisꢀclearedꢀtoꢀ0ꢀbyꢀErase/Programꢀ
Resumeꢀ(7Ah)ꢀinstructionꢀasꢀwellꢀasꢀaꢀpowerꢁdown,ꢀpowerꢁupꢀcycle.ꢀ
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11.1.8ꢀQuadꢀEnableꢀ(QE)ꢀ
Theꢀ Quadꢀ Enableꢀ (QE)ꢀbitꢀisꢀ aꢀ nonꢁvolatileꢀ read/writeꢀ bitꢀinꢀ theꢀstatusꢀ registerꢀ (S9)ꢀ thatꢀ allowsꢀ
Quadꢀoperation.ꢀWhenꢀtheꢀQEꢀbitꢀisꢀsetꢀtoꢀaꢀ0ꢀstateꢀ(factoryꢀdefault)ꢀtheꢀ/WPꢀpinꢀandꢀ/Holdꢀareꢀ
enabled.ꢀWhenꢀtheꢀQEꢀpinꢀisꢀsetꢀtoꢀaꢀ1ꢀtheꢀQuadꢀIO2ꢀandꢀIO3ꢀpinsꢀareꢀenabled.ꢀ
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WARNINGꢀ:ꢀTheꢀQEꢀbitꢀshouldꢀneverꢀbeꢀsetꢀtoꢀaꢀ1ꢀduringꢀstandardꢀSPIꢀorꢀDualꢀSPIꢀoperationꢀ
ifꢀtheꢀ/WPꢀorꢀ/HOLDꢀpinsꢀareꢀtiedꢀdirectlyꢀtoꢀtheꢀpowerꢀsupplyꢀorꢀground.ꢀ
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preliminary(Aug.18.2010)ꢀ ꢀ ꢀ ꢀ
14ꢀ
FIDELIX [ FIDELIX ]
