E S I
E S I
Excel Semiconductor inc.
3.3V
Table 8. Test Specifications
2.7k
Ω
Test Condition
70
90
120
Device
Under
Test
Output Load
1TTL gate
100 pF
C
L
Output Load Capacitance, CL (including jig
capacitance)
30 pF
100 pF
6.2kΩ
Input Rise and Fall Times
5 ns
0.0 - 3.0 V
1.5 V
Input Pulse Levels
Input timing measurement reference levels
Output timing measurement reference levels
Figure 14. Test Setup
1.5 V
Note: Diodes are IN3064 or equivalent
Key To Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0V
1.5V Output
Input 1.5V
Measurement Level
0.0V
Figure 15. Input Waveforms and Measurement Levels
29
Rev. 1D January 5, 2006
ES29LV800D