XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
6.7.9 COMMAND OR RESPONSE BIT (C/R) ...................................................................................................................... 165
6.7.10 SERVICE ACCESS POINT IDENTIFIER (SAPI) ...................................................................................................... 165
6.7.11 TERMINAL ENDPOINT IDENTIFIER (TEI) ............................................................................................................... 165
6.7.12 CONTROL FIELD ...................................................................................................................................................... 165
6.7.13 FRAME CHECK SEQUENCE (FCS) FIELD ............................................................................................................. 165
6.7.14 TRANSPARENCY (ZERO STUFFING) ..................................................................................................................... 166
6.8 TRANSMIT SLC®96 DATA LINK CONTROLLER .......................................................................................... 167
6.9 D/E TIME SLOT TRANSMIT HDLC CONTROLLER BLOCK V5.1 OR V5.2 INTERFACE ............................ 168
6.10 AUTOMATIC PERFORMANCE REPORT (APR) .......................................................................................... 168
6.10.1 BIT VALUE INTERPRETATION ............................................................................................................................... 168
7.0 OVERHEAD INTERFACE BLOCK ...................................................................................................... 170
7.1 DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .......................................................................... 170
7.1.1 DESCRIPTION OF THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .............................................. 170
7.1.2 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE FACILITY DATA
LINK (FDL) BITS IN ESF FRAMING FORMAT MODE ............................................................................................... 170
7.1.3 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE SIGNALING
FRAMING (FS) BITS IN N OR SLC®96 FRAMING FORMAT MODE ........................................................................ 172
7.1.4 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE REMOTE SIG-
NALING (R) BITS IN T1DM FRAMING FORMAT MODE ........................................................................................... 173
7.2 DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ......................................................................... 173
7.2.1 DESCRIPTION OF THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................. 174
7.2.2 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE FACILITY
DATA LINK (FDL) BITS IN ESF FRAMING FORMAT MODE .................................................................................... 174
7.2.3 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE SIGNALING
FRAMING (FS) BITS IN N OR SLC®96 FRAMING FORMAT MODE ........................................................................ 175
7.2.4 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE REMOTE
SIGNALING (R) BITS IN T1DM FRAMING FORMAT MODE ..................................................................................... 176
7.3 E1 OVERHEAD INTERFACE BLOCK ............................................................................................................ 177
7.4 E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ............................................................................. 177
7.4.1 DESCRIPTION OF THE E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ................................................. 177
7.4.2 CONFIGURE THE E1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT SE-
QUENCE IN E1 FRAMING FORMAT MODE .............................................................................................................. 178
7.5 E1 RECEIVE OVERHEAD INTERFACE ......................................................................................................... 180
7.5.1 DESCRIPTION OF THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................... 180
7.5.2 CONFIGURE THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT
SEQUENCE IN E1 FRAMING FORMAT MODE .......................................................................................................... 181
8.0 LIU TRANSMIT PATH ......................................................................................................................... 183
8.1 TRANSMIT DIAGNOSTIC FEATURES ........................................................................................................... 183
8.1.1 TAOS (TRANSMIT ALL ONES) .................................................................................................................................. 183
8.1.2 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ......................................................................................................... 184
8.1.3 NETWORK LOOP UP CODE ...................................................................................................................................... 184
8.1.4 NETWORK LOOP DOWN CODE ............................................................................................................................... 184
8.1.5 QRSS GENERATION .................................................................................................................................................. 185
8.2 T1 LONG HAUL LINE BUILD OUT (LBO) ...................................................................................................... 185
8.3 T1 SHORT HAUL LINE BUILD OUT (LBO) .................................................................................................... 186
8.3.1 ARBITRARY PULSE GENERATOR ........................................................................................................................... 186
8.3.2 DMO (DIGITAL MONITOR OUTPUT) ......................................................................................................................... 187
8.3.3 TRANSMIT JITTER ATTENUATOR ........................................................................................................................... 187
8.4 LINE TERMINATION (TTIP/TRING) ................................................................................................................ 188
9.0 LIU RECEIVE PATH ............................................................................................................................ 189
9.1 LINE TERMINATION (RTIP/RRING) ............................................................................................................... 189
9.1.1 CASE 1: INTERNAL TERMINATION .......................................................................................................................... 189
9.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 189
9.1.3 EQUALIZER CONTROL ............................................................................................................................................. 190
9.1.4 CABLE LOSS INDICATOR ......................................................................................................................................... 190
9.2 RECEIVE SENSITIVITY ................................................................................................................................... 191
9.2.1 AIS (ALARM INDICATION SIGNAL) .......................................................................................................................... 191
9.2.2 NLCD (NETWORK LOOP CODE DETECTION) ......................................................................................................... 191
9.2.3 FLSD (FIFO LIMIT STATUS DETECTION) ................................................................................................................ 192
9.2.4 RECEIVE JITTER ATTENUATOR .............................................................................................................................. 192
9.2.5 RXMUTE (RECEIVER LOS WITH DATA MUTING) ................................................................................................... 192
10.0 THE E1 TRANSMIT/RECEIVE FRAMER .......................................................................................... 194
10.1 DESCRIPTION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK ................ 194
10.1.1 BRIEF DISCUSSION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT
II
EXAR [ EXAR CORPORATION ]
