XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
JANUARY 2008
REV. 1.0.1
frames from the incoming T1/E1/J1 data stream and
write the contents into the Receive HDLC buffers.
The framer also contains a Transmit and Overhead
Data Input port, which permits Data Link Terminal
Equipment direct access to the outbound T1/E1/J1
frames. Likewise, a Receive Overhead output data
port permits Data Link Terminal Equipment direct
access to the Data Link bits of the inbound T1/E1/J1
frames.
GENERAL DESCRIPTION
The XRT86L30 is a single channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated
solution featuring R3 technology (Relayless,
Reconfigurable, Redundancy).
The physical
interface is optimized with internal impedance, and
with the patented pad structure, the XRT86L30
provides protection from power failures and hot
swapping.
The XRT86L30 fully meets all of the latest T1/E1/J1
specifications:
ANSI T1/E1.107-1988, ANSI T1/
The XRT86L30 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. The framer has a framing synchronizer
and transmit-receive slip buffers. The slip buffers can
be independently enabled or disabled as required
and can be configured to frame to the common DS1/
E1/J1 signal formats.
E1.403-1999, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
The Framer block contains a Transmit and Receive
T1/E1/J1 Framing function. There are 3 Transmit
HDLC controllers which encapsulate contents of the
Transmit HDLC buffers into LAPD Message frames.
There are 3 Receive HDLC controllers which extract
the payload content of Receive LAPD Message
Applications and Features (next page)
FIGURE 1. XRT86L30 1-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO
External Data
Link Controller
Local PCM
Highway
Tx Overhead In
Rx Overhead Out
XRT86L30
1:2 Turns Ratio
1:1 Turns Ratio
TTIP
2-Frame
Slip Buffer
Elastic Store
Tx Serial
Data In
Tx LIU
Interface
Tx Framer
Rx Framer
TRING
Tx Serial
Clock
LLB
LB
RTIP
2-Frame
Slip Buffer
Elastic Store
Rx Serial
Data Out
Rx LIU
Interface
RRING
Rx Serial
Clock
LIU &
Loopback
Control
PRBS
Generator &
Analyser
HDLC/LAPD
Controllers
Performance
Monitor
RxLOS
Line Side
8kHz sync
OSC
DMA
Interface
Microprocessor
Interface
Signaling &
Alarms
JTAG
Back Plane
1.544-16.384 Mbit/s
WR
ALE_AS
RD
4
3
µP
Select
INT
System (Terminal) Side
D[7:0]
A[11:0]
RDY_DTACK
TxON
Intel/Motorola µP
Configuration, Control &
Status Monitor
Memory
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
EXAR [ EXAR CORPORATION ]
