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XRT86L30IV 参数 Datasheet PDF下载

XRT86L30IV图片预览
型号: XRT86L30IV
PDF下载: 下载PDF文件 查看货源
内容描述: 单一T1 / E1 / J1成帧器/ LIU COMBO [SINGLE T1/E1/J1 FRAMER/LIU COMBO]
分类和应用:
文件页数/大小: 284 页 / 1793 K
品牌: EXAR [ EXAR CORPORATION ]
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XRT86L30  
SINGLE T1/E1/J1 FRAMER/LIU COMBO  
REV. 1.0.1  
LIST OF PARAGRAPHS  
1.0 PIN LIST ...................................................................................................................................................4  
2.0 PIN DESCRIPTIONS ................................................................................................................................8  
3.0 MICROPROCESSOR INTERFACE BLOCK ..........................................................................................21  
3.0.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ....................................................................................... 21  
3.1 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ..................................................................24  
3.2 MOTOROLA MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ..........................................................26  
3.2.1 DMA READ/WRITE OPERATIONS .............................................................................................................................. 28  
3.3 MEMORY MAPPED I/O ADDRESSING ............................................................................................................30  
3.4 DESCRIPTION OF THE CONTROL REGISTERS ............................................................................................31  
3.4.1 REGISTER DESCRIPTIONS ......................................................................................................................................... 37  
3.5 PROGRAMMING THE LINE INTERFACE UNIT (LIU SECTION) ...................................................................118  
3.6 THE INTERRUPT STRUCTURE WITHIN THE FRAMER ...............................................................................138  
3.6.1 CONFIGURING THE INTERRUPT SYSTEM, AT THE FRAMER LEVEL .................................................................. 141  
4.0 GENERAL DESCRIPTION AND INTERFACE .....................................................................................144  
4.1 PHYSICAL INTERFACE ..................................................................................................................................144  
4.2 R3 TECHNOLOGY (RELAYLESS / RECONFIGURABLE / REDUNDANCY) ................................................145  
4.2.1 LINE CARD REDUNDANCY ....................................................................................................................................... 145  
4.2.2 TYPICAL REDUNDANCY SCHEMES ........................................................................................................................ 145  
4.2.3 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 145  
4.2.4 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 145  
4.2.5 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ..................................................................................... 146  
4.3 POWER FAILURE PROTECTION ...................................................................................................................147  
4.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ................................................................................147  
4.5 NON-INTRUSIVE MONITORING .....................................................................................................................147  
4.6 T1/E1 SERIAL PCM INTERFACE ...................................................................................................................148  
4.7 T1/E1 FRACTIONAL INTERFACE ..................................................................................................................149  
4.8 T1/E1 TIME SLOT SUBSTITUTION AND CONTROL .....................................................................................150  
4.9 ROBBED BIT SIGNALING/CAS SIGNALING .................................................................................................151  
4.10 OVERHEAD INTERFACE ..............................................................................................................................153  
4.11 FRAMER BYPASS MODE .............................................................................................................................154  
4.12 HIGH-SPEED NON-MULTIPLEXED INTERFACE ........................................................................................155  
4.13 HIGH-SPEED MULTIPLEXED INTERFACE .................................................................................................156  
5.0 LOOPBACK MODES OF OPERATION ...............................................................................................157  
5.1 LIU PHYSICAL INTERFACE LOOPBACK DIAGNOSTICS ............................................................................157  
5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 157  
5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 157  
5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 158  
5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 158  
5.1.5 FRAMER REMOTE LINE LOOPBACK ...................................................................................................................... 158  
5.1.6 FRAMER PAYLOAD LOOPBACK ............................................................................................................................. 159  
5.1.7 FRAMER LOCAL LOOPBACK ................................................................................................................................... 159  
6.0 HDLC CONTROLLERS AND LAPD MESSAGES ...............................................................................160  
6.1 PROGRAMMING SEQUENCE FOR SENDING LESS THAN 96-BYTE MESSAGES ....................................160  
6.2 PROGRAMMING SEQUENCE FOR SENDING LARGE MESSAGES ...........................................................160  
6.3 PROGRAMMING SEQUENCE FOR RECEIVING LAPD MESSAGES ...........................................................161  
6.4 SS7 (SIGNALING SYSTEM NUMBER 7) FOR ESF IN DS1 ONLY ................................................................161  
6.5 DS1/E1 DATALINK TRANSMISSION USING THE HDLC CONTROLLERS .................................................162  
6.6 TRANSMIT BOS (BIT ORIENTED SIGNALING) PROCESSOR .....................................................................162  
6.6.1 DESCRIPTION OF BOS .............................................................................................................................................. 162  
6.6.2 PRIORITY CODEWORD MESSAGE .......................................................................................................................... 162  
6.6.3 COMMAND AND RESPONSE INFORMATION .......................................................................................................... 162  
6.7 TRANSMIT MOS (MESSAGE ORIENTED SIGNALING) PROCESSOR ........................................................163  
6.7.1 DISCUSSION OF MOS ............................................................................................................................................... 163  
6.7.2 PERIODIC PERFORMANCE REPORT ...................................................................................................................... 163  
6.7.3 TRANSMISSION-ERROR EVENT .............................................................................................................................. 164  
6.7.4 PATH AND TEST SIGNAL IDENTIFICATION MESSAGE ......................................................................................... 164  
6.7.5 FRAME STRUCTURE ................................................................................................................................................. 164  
6.7.6 FLAG SEQUENCE ...................................................................................................................................................... 164  
6.7.7 ADDRESS FIELD ........................................................................................................................................................ 165  
6.7.8 ADDRESS FIELD EXTENSION BIT (EA) ................................................................................................................... 165  
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