XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
LIST OF FIGURES
Figure 1.: XRT86L30 1-channel DS1 (T1/E1/J1) Framer/LIU Combo ...............................................................................1
Figure 2.: Simplified Block Diagram of the Microprocessor Interface Block ....................................................................21
Figure 3.: Intel µP Interface Signals During Programmed I/O Read and Write Operations .............................................25
Figure 4.: Motorola µP Interface Signals During Programmed I/O Read and Write Operations ......................................27
Figure 5.: Motorola 68K µP Interface Signals During Programmed I/O Read and Write Operations ..............................28
Figure 6.: DMA Mode for the XRT86L30 and a Microprocessor ......................................................................................29
Figure 7.: LIU Transmit Connection Diagram Using Internal Termination .....................................................................144
Figure 8.: LIU Receive Connection Diagram Using Internal Termination .....................................................................144
Figure 9.: Simplified Block Diagram of the Transmit Interface for 1:1 and 1+1 Redundancy ........................................145
Figure 10.: Simplified Block Diagram of the Receive Interface for 1:1 and 1+1 Redundancy .......................................146
Figure 11.: Simplified Block Diagram of a Non-Intrusive Monitoring Application ...........................................................147
Figure 12.: Transmit T1/E1 Serial PCM Interface ..........................................................................................................148
Figure 13.: Receive T1/E1 Serial PCM Interface ...........................................................................................................148
Figure 14.: T1 Fractional Interface .................................................................................................................................149
Figure 15.: T1/E1 Time Slot Substitution and Control .................................................................................................... 150
Figure 16.: Robbed Bit Signaling / CAS Signaling .........................................................................................................151
Figure 17.: ESF / CAS External Signaling Bus ..............................................................................................................151
Figure 18.: SF / SLC-96 or 4-code Signaling in ESF / CAS External Signaling Bus ......................................................152
Figure 19.: T1/E1 Overhead Interface ...........................................................................................................................153
Figure 20.: T1 External Overhead Datalink Bus ............................................................................................................153
Figure 21.: E1 Overhead External Datalink Bus ............................................................................................................154
Figure 22.: Simplified Block Diagram of the Framer Bypass Mode ...............................................................................154
Figure 23.: T1 High-Speed Non-Multiplexed Interface ...................................................................................................155
Figure 24.: E1 High-Speed Non-Multiplexed Interface ..................................................................................................155
Figure 25.: Transmit High-Speed Bit Multiplexed Block Diagram ..................................................................................156
Figure 26.: Receive High-Speed Bit Multiplexed Block Diagram ...................................................................................156
Figure 27.: Simplified Block Diagram of Local Analog Loopback ..................................................................................157
Figure 28.: Simplified Block Diagram of Remote Loopback ...........................................................................................157
Figure 29.: Simplified Block Diagram of Digital Loopback .............................................................................................158
Figure 30.: Simplified Block Diagram of Dual Loopback ................................................................................................158
Figure 31.: Simplified Block Diagram of the Framer Remote Line Loopback ................................................................158
Figure 32.: Simplified Block Diagram of the Framer Local Loopback ............................................................................159
Figure 33.: Simplified Block Diagram of the Framer Local Loopback ............................................................................159
Figure 34.: HDLC Controllers .........................................................................................................................................160
Figure 35.: LAPD Frame Structure ................................................................................................................................163
Figure 36.: Block Diagram of the DS1 Transmit Overhead Input Interface of the XRT86L30 .......................................170
Figure 37.: DS1 Transmit Overhead Input Interface Timing in ESF Framing Format mode ..........................................172
Figure 38.: DS1 Transmit Overhead Input Timing in N or SLC®96 Framing Format Mode ..........................................173
Figure 39.: DS1 Transmit Overhead Input Interface module in T1DM Framing Format mode ......................................173
Figure 40.: Block Diagram of the DS1 Receive Overhead Output Interface of XRT86L30 ............................................174
Figure 41.: DS1 Receive Overhead Output Interface module in ESF framing format mode .........................................175
Figure 42.: DS1 Receive Overhead Output Interface Timing in N or SLC®96 Framing Format mode ..........................176
Figure 43.: DS1 Receive Overhead Output Interface Timing in T1DM Framing Format mode .....................................177
Figure 44.: Block Diagram of the E1 Transmit Overhead Input Interface of XRT86L30 ................................................178
Figure 45.: E1 Transmit Overhead Input Interface Timing .............................................................................................180
Figure 46.: Block Diagram of the E1 Receive Overhead Output Interface of XRT86L30 ..............................................180
Figure 47.: E1 Receive Overhead Output Interface Timing ...........................................................................................182
Figure 48.: TAOS (Transmit All Ones) ...........................................................................................................................183
Figure 49.: Simplified Block Diagram of the ATAOS Function .......................................................................................184
Figure 50.: Network Loop Up Code Generation .............................................................................................................184
Figure 51.: Network Loop Down Code Generation ........................................................................................................184
Figure 52.: Long Haul Line Build Out with -7.5dB Attenuation .......................................................................................185
Figure 53.: Long Haul Line Build Out with -15dB Attenuation ........................................................................................185
Figure 54.: Long Haul Line Build Out with -22.5dB Attenuation .....................................................................................186
Figure 55.: Arbitrary Pulse Segment Assignment .......................................................................................................... 187
Figure 56.: Typical Connection Diagram Using Internal Termination ............................................................................188
Figure 57.: Typical Connection Diagram Using Internal Termination ...........................................................................189
Figure 58.: Typical Connection Diagram Using One External Fixed Resistor ...............................................................190
V
EXAR [ EXAR CORPORATION ]
