XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
JTAG
S
IGNAL
NAME
P
IN
#
TYPE
DESCRIPTION
JTAG_Ring
JTAG_Tip
10
11
I
I
JTAG_Ring Test Pin
JTAG_Tip Test Pin
MICROPROCESSOR INTERFACE
(Framer Channel Number indicated by )
S
IGNAL
NAME
P
IN
#
TYPE
DESCRIPTION
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
69
70
90
91
I/O
Bidirectional Microprocessor Data Bus
Data[7:0] is a bi-directional data bus used for read and write operations.
NOTE: This bus is used as the bi-directional data port for storing and retrieving
information through the DMA interface if enabled.
101
103
104
106
REQ0
64
O
DMA Cycle Request Output—DMA Controller 0 (Write):
The Framer asserts this output pin (toggles it "Low") when at least one of the
Transmit HDLC buffers are empty and can receive one more HDLC message.
The Framer negates this output pin (toggles it “High”) when the HDLC buffer
can no longer receive another HDLC message.
DMA Cycle Request Output—DMA Controller 1 (Read):
REQ1
61
The Framer asserts this output pin (toggles it "Low") when one of the Receive
HDLC buffer contains a complete HDLC message that needs to be read by the
µC/µP.
The Framer negates this output pin (toggles it High) when the Receive HDLC
buffers are depleted.
INT
96
68
O
I
Interrupt Request Output:
The Framer will assert this active "Low" output (toggles it "Low"), to the local µP,
anytime it requires interrupt service.
PCLK
Microprocessor Clock Input:
This clock signal is the Microprocessor Interface System clock. This clock signal
is used for synchronous/DMA data transfer. The maximum frequency of this
clock signal is 33MHz.
iADDR
fADDR
124
123
I
I
This Pin Must be Tied “Low” for Normal Operation.
This Pin Must be Tied “High” for Normal Operation.
17
EXAR [ EXAR CORPORATION ]
