XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
MICROPROCESSOR INTERFACE
(Framer Channel Number indicated by )
REV. 1.0.1
S
IGNAL
N
AME
P
IN
#
TYPE
DESCRIPTION
CS
108
I
Microprocessor Interface—Chip Select Input:
The Microprocessor/Microcontroller must assert this input pin (toggle it "Low") in
order to exchange data with the Framer.
Note: For the 68K MPU, this signal is generated by address decode and
address strobe.
RD
71
107
62
I
I
I
Microprocessor Interface—Read Strobe Input:
The exact behavior of this pin depends upon the type of Microprocessor/Micro-
controller the Framer has been configured to interface to, as defined by the
µPTYPE[2:0] pins.
WR
Microprocessor Interface—Write Strobe Input
The exact behavior of this pin depends upon the type of Microprocessor/Micro-
controller the Framer has been configured to interface to, as defined by the
µPTYPE[2:0] pins.
ACK0
DMA Cycle Acknowledge Input—DMA Controller 0 (Write):
The external DMA Controller will assert this input pin “Low” when the following
two conditions are met:
a. After the DMA Controller, within the Framer has asserted (toggled “Low”), the
Req_0 output signal.
b. When the external DMA Controller is ready to transfer data from external
memory to the selected Transmit HDLC buffer.
At this point, the DMA transfer between the external memory and the selected
Transmit HDLC buffer may begin.
After completion of the DMA cycle, the external DMA Controller will negate this
input pin after the DMA Controller within the Framer has negated the Req_0 out-
put pin. The external DMA Controller must do this in order to acknowledge the
end of the DMA cycle.
DMA Cycle Acknowledge Input—DMA Controller 1 (Read):
The external DMA Controller asserts this input pin “Low” when the following two
conditions are met:
ACK1
65
a. After the DMA Controller, within the Framer has asserted (toggled "Low"), the
Req_1 output signal.
b. When the external DMA Controller is ready to transfer data from the selected
Receive HDLC buffer to external memory.
At this point, the DMA transfer between the selected Receive HDLC buffer and
the external memory may begin.
After completion of the DMA cycle, the external DMA Controller will negate this
input pin after the DMA Controller within the Framer has negated the Req_1 out-
put pin. The external DMA Controller will do this in order to acknowledge the
end of the DMA cycle.
BLAST
RESET
100
85
I
I
Last Cycle of Burst Indicator Input:
The Microprocessor asserts this pin “Low”when it is performing its last read or
write cycle, within a burst operation.
Hardware Reset Input
Reset is an active low input. If this pin is pulled “Low” for more than 10µS, the
device will be reset, and the internal registers will be reset to their default val-
ues.
19
EXAR [ EXAR CORPORATION ]
