XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
The Receive Data Link Source Select bits of the Receive Data Link Select Register (RDLSR) controls the
destination of R bits in T1DM framing format mode. The table below shows configuration of the Receive Data
Link Source Select bits of the Receive Data Link Select Register (RDLSR).
RECEIVE DATA LINK SELECT REGISTER (RDLSR) (ADDRESS = 0X010AH)
B
IT
B
IT
N
AME
B
IT
TYPE
BIT DESCRIPTION
N
UMBER
1-0
Receive Data Link
Source Select
R/W
00 - The extracted Facility Data Link bits are stored in either the LAPD con-
troller or the SLC 96 buffer. At the same time, the extracted Facility Data
®
Link bits are outputted from the framer through the Receive Serial Data
Output Interface via the RxSer_n pins.
01 - The extracted Facility Data Link bits are outputted from the framer
through the Receive Serial Data Output Interface via the RxSer_n pins.
10 - The extracted Facility Data Link bits are outputted from the framer
through the Receive Overhead Output Interface via the RxOH_n pins. At
the same time, the extracted Facility Data Link bits are outputted from the
framer through the Receive Serial Data Output Interface via the RxSer_n
pins.
11 - The Facility Data Link bits are forced to one by the framer.
If the Receive Data Link Source Select bits of the Receive Data Link Select Register are set to 10, the Receive
Overhead Output Interface Block outputs the R bits extracted from the incoming T1 data stream. Since R bit
presents in Timeslot 24 of every T1DM frame, therefore, bandwidth of T1DM data link channel is 8KHz.
Figure 43 below shows the timing diagram of the output signals associated with the DS1 Receive Overhead
Output Interface module in T1DM framing format mode.
FIGURE 43. DS1 RECEIVE OVERHEAD OUTPUT INTERFACE TIMING IN T1DM FRAMING FORMAT MODE
7.3
E1 Overhead Interface Block
The XRT86L30 has the ability to extract or insert E1 data link information from or into the E1 National bit
sequence. The source and destination of these inserted and extracted data link bits would be from either the
internal HDLC Controller or the external device accessible through E1 Overhead Interface Block. The
operation of the Transmit Overhead Input Interface Block and the Receive Overhead Output Interface Block
will be discussed separately.
7.4
E1 Transmit Overhead Input Interface Block
7.4.1
Description of the E1 Transmit Overhead Input Interface Block
177
EXAR [ EXAR CORPORATION ]
