XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
Figure 45 below shows the timing diagram of the input and output signals associated with the E1 Transmit
Overhead Input Interface module in E1 framing format mode.
FIGURE 45. E1 TRANSMIT OVERHEAD INPUT INTERFACE TIMING
7.5
E1 Receive Overhead Interface
Description of the E1 Receive Overhead Output Interface Block
7.5.1
The E1 Receive Overhead Output Interface Block will allow an external device to be the consumer of the E1
National bit sequence. This interface provides interface signals and required interface timing to shift out proper
data link information at proper time.
The Receive Overhead Output Interface for a given Framer consists of two signals.
•
•
RxOHClk_n: The Receive Overhead Output Interface Clock Output signal
RxOH_n: The Receive Overhead Output Interface Output signal.
The Receive Overhead Output Interface Clock Output pin (RxOHCLK_n) generates a rising clock edge for
each National bit that is configured to carry Data Link information according to setting of the framer. The data
link bits extracted from the incoming E1 frames are outputted from the Receive Overhead Output Interface
Output pin (RxOH_n) before the rising edge of RxOHClk_n. The Data Link equipment should sample and latch
the data link bits at the rising edge of RxOHClk_n.
The figure below shows block diagram of the Receive Overhead Output Interface of XRT86L30.
FIGURE 46. BLOCK
D
IAGRAM OF THE E1 RECEIVE
O
VERHEAD
O
UTPUT
INTERFACE OF XRT86L30
RxOH_n
Receive
Overhead Output
Interface
From Receive
Framer Block
RxOHClk_n
180
EXAR [ EXAR CORPORATION ]
