XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
TABLE 110: T1/E1 FRAME
CHECK
SEQUENCE
ERROR COUNTER 3
R
EGISTER 527
IT
PMON LAPD3 FRAME
C
HECK
S
EQUENCE
E
RROR OUNTER 3 (LFCSEC3)
C
HEX ADDRESS: 0X092C
B
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
FCSEC3[7]
FCSEC3[6]
FCSEC3[5]
FCSEC3[4]
FCSEC3[3]
FCSEC3[2]
FCSEC3[1]
FCSEC3[0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Frame Check Sequence error Accumulation Counter 3.
Note: 8-bit Counter accumulates the times of occurrence of receive
frame check sequence error detected by LAPD3 controller.
6
5
4
3
2
1
0
TABLE 111: BLOCK
INTERRUPT
STATUS
REGISTER
R
EGISTER 528
IT
B
LOCK
I
NTERRUPT TATUS
S
R
EGISTER (BISR)
HEX ADDRESS: 0X0B00
B
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
Sa6
RO
0
Sa6 Interrupt Status
6
5
LBCODE
RO
0
0
Loopback Code Interrupt
RxClkLOS
RUR
RxClk Los Interrupt Status
Indicates if Framer n has experienced a Loss of Recovered Clock
interrupt since last read of this register.
0 = Loss of Recovered Clock interrupt has not occurred since last
read of this register
1 = Loss of Recovered Clock interrupt has occurred since last read
of this register.
4
3
ONESEC
HDLC
RUR
RO
0
0
One Second Interrupt Status
Indicates if the XRT86L30 has experienced a One Second interrupt
since the last read of this register.
0 = No outstanding One Second interrupts awaiting service
1 = Outstanding One Second interrupt awaits service
HDLC Block Interrupt Status
Indicates if the HDLC block has an interrupt request awaiting ser-
vice.
0 = No outstanding interrupt requests awaiting service
1 = HDLC Block has an interrupt request awaiting service. Interrupt
Service routine should branch to and read Data LInk Status Register
(address xA,06).
NOTE: This bit-field will be reset to 0 after the microprocessor has
performed a read to the Data Link Status Register.
95
EXAR [ EXAR CORPORATION ]
