XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
TABLE 107: T1/E1 EXCESSIVE
Z
ERO
VIOLATION COUNTER MSB
R
R
R
EGISTER 524
T1/E1 EXCESSIVE
Z
ERO
V
IOLATION OUNTER MSB (EZVCU)
C
HEX ADDRESS: 0X0910
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
EZVC[15]
EZVC[14]
EZVC[13]
EZVC[12]
EZVC[11]
EZVC[10]
EZVC[9]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
These eight bits represent the MSB for the 16-bit Excessive Zero
Violation Counter.
6
5
4
3
2
1
0
EZVC[8]
TABLE 108: T1/E1 EXCESSIVE
Z
ERO
VIOLATION COUNTER LSB
EGISTER 525
IT
T1/E1 EXCESSIVE
Z
ERO
V
IOLATION OUNTER MSB (EZVCL)
C
HEX ADDRESS: 0X0911
B
F
EZVC[7]
EZVC[6]
EZVC[5]
EZVC[4]
EZVC[3]
EZVC[2]
EZVC[1]
EZVC[0]
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
These eight bits represent the LSB for the 16-bit Excessive Zero
Violation Counter.
6
5
4
3
2
1
0
T
ABLE 109: T1/E1 FRAME
C
HECK
S
EQUENCE
ERROR COUNTER 2
EGISTER 526
IT
PMON LAPD2 FRAME
C
HECK
S
EQUENCE
E
RROR OUNTER 2 (LFCSEC2)
C
HEX ADDRESS: 0X091C
B
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
FCSEC2[7]
FCSEC2[6]
FCSEC2[5]
FCSEC2[4]
FCSEC2[3]
FCSEC2[2]
FCSEC2[1]
FCSEC2[0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Frame Check Sequence error Accumulation Counter 2.
Note: 8-bit Counter accumulates the times of occurrence of receive
frame check sequence error detected by LAPD2 controller.
6
5
4
3
2
1
0
94
EXAR [ EXAR CORPORATION ]
