XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
TABLE 98: PMON T1/E1 RECEIVE
F
AR-END BLOCK
ERROR COUNTER - MSB
R
EGISTER 515
PMON RECEIVE
F
AR-END
B
LOCK
E
RROR
C
OUNTER (RFEBECU)
HEX ADDRESS: 0X0907
B
IT
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
RFEBEC[15]
RFEBEC[14]
RFEBEC[13]
RFEBEC[12]
RFEBEC[11]
RFEBEC[10]
RFEBEC[9]
RFEBEC[8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
These eight bits represent the MSB for the 16-bit Receive Far-End
Block Error counter.
6
5
4
3
2
1
0
T
ABLE 99: PMON T1/E1 RECEIVE
F
AR
E
ND
B
LOCK
E
RROR
C
OUNTER
EX ADDRESS: 0X0908
R
EGISTER 516
PMON RECEIVE
F
AR
E
ND
BLOCK
E
RROR
C
OUNTER (RFEBECL)
H
B
IT
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
RFEBEC[7]
RFEBEC[6]
RFEBEC[5]
RFEBEC[4]
RFEBEC[3]
RFEBEC[2]
RFEBEC[1]
RFEBEC[0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
These eight bits represent the LSB for the 16-bit Receive Far-End
Block Error counter.
6
5
4
3
2
1
0
Note: Counter contains the 16-bit far-end block error event. Counter
will increment once each time the received E-bit is set to zero. The
counter is disabled during loss of sync at either the FAS or CRC-4
level and it will continue to count if loss of multiframe sync occurs at
the CAS level.
TABLE 100: PMON T1/E1 RECEIVE
S
LIP
COUNTER
R
EGISTER 517
IT
PMON RECEIVE
S
LIP
C
OUNTER (RSC)
HEX ADDRESS: 0X0909
B
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
RSC[7]
RSC[6]
RSC[5]
RSC[4]
RSC[3]
RSC[2]
RSC[1]
RSC[0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Note: counter contains the 8-bit receive buffer slip event. A slip
event is defined as a replication or deletion of a T1/E1 frame by the
receiving slip buffer.
6
5
4
3
2
1
0
Note: A 16 bit counter which counts the occurrence of a bipolar vio-
lation on the receive data line. This counter is of sufficient length so
that the probability of counter saturation over a one second interval
at a 10 -3-Bit Error Rate (BER) is less than 0.001%.
91
EXAR [ EXAR CORPORATION ]
