XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
T
ABLE 90: LAPD BUFFER 1 CONTROL
R
EGISTER
EX ADDRESS: 0X0700 TO 0X0760
R
EGISTER 412-507
UNCTION
LAPD BUFFER 0 CONTROL
R
EGISTER (LAPDBCR1)
H
B
IT
F
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7-0 LAPD Buffer 1
R/W
0
LAPD Buffer 1 (96-Bytes)
This register is used to transmit and receive LAPD messages within
buffer 1 of the HDLC controller chosen in the LAPD Select Register
(0x011B). When writing to buffer 1, the message is inserted into the
outgoing LAPD frame and the data cannot be retrieved. After
detecting the Rx end of transfer interrupt, the extracted LAPD mes-
sage is available to be read.
NOTE
:
When writing or reading from Buffer 1, the register is
automatically incremented such that 0x0700 can be written
to or read from continuously.
T
ABLE 91: PMON T1/E1 RECEIVE
L
INE
C
ODE
(
BIPOLAR) VIOLATION
C
OUNTER
EX DDRESS: 0X0900
R
EGISTER 508 PMON RECEIVE
L
INE
C
ODE
(
BIPOLAR) VIOLATION
C
OUNTER MSB (RLCVCU)
H
A
B
IT
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
RLCVC[15]
RLCVC[14]
RLCVC[13]
RLCVC[12]
RLCVC[11]
RLCVC[10]
RLCVC[9]
RLCVC[8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
These eight bits represent the MSB for the 16-bit Line Code Viola-
tion counter.
6
5
4
3
2
1
0
TABLE 92: PMON T1/E1 RECEIVE
L
INE
C
ODE
(BIPOLAR) VIOLATION
COUNTER
R
EGISTER 509
IT
PMON RECEIVE
L
INE
C
ODE
(
BIPOLAR) VIOLATION
C
OUNTER LSB (RLCVCL) HEX ADDRESS: 0X0901
B
F
UNCTION YPE
T
D
EFAULT
DESCRIPTION-OPERATION
7
RLCVC[7]
RLCVC[6]
RLCVC[5]
RLCVC[4]
RLCVC[3]
RLCVC[2]
RLCVC[1]
RLCVC[0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
These eight bits represent the LSB for the 16-bit Line Code Violation
counter.
6
5
4
3
2
1
0
88
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