XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
.
T
ABLE 93: PMON T1/E1 RECEIVE
F
RAMING
A
LIGNMENT
B
IT
E
RROR
C
OUNTER
EX ADDRESS: 0X0902
R
EGISTER 510
IT
PMON RECEIVE
FRAMING
A
LIGNMENT
E
RROR
C
OUNTER MSB (RFAECU)
H
B
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
RFAEC[15]
RFAEC[14]
RFAEC[13]
RFAEC[12]
RFAEC[11]
RFAEC[10]
RFAEC[9]
RFAEC[8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
These eight bits represent the MSB for the 16-bit Receive Framing
Alignment Error counter.
6
5
4
3
2
1
0
.
T
ABLE 94: PMON T1/E1 RECEIVE
F
RAMING
A
LIGNMENT
B
IT
E
RROR
C
OUNTER
EX ADDRESS: 0X0903
R
EGISTER 511
PMON RECEIVE
F
RAMING
ALIGNMENT
E
RROR
C
OUNTER LSB (RFAECL)
H
B
IT
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
RFAEC[7]
RFAEC[6]
RFAEC[5]
RFAEC[4]
RFAEC[3]
RFAEC[2]
RFAEC[1]
RFAEC[0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
These eight bits represent the LSB for the 16-bit Receive Framing
Alignment Error counter.
6
5
4
3
2
1
0
T
ABLE 95: PMON T1/E1 RECEIVE
S
EVERELY
E
RRORED
F
RAME
C
OUNTER
EX ADDRESS: 0X0904
R
EGISTER 512
PMON RECEIVE
S
EVERELY
E
RRORED RAME
F
C
OUNTER (RSEFC)
H
B
IT
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
6
5
4
3
2
1
0
RSEFC[7]
RSEFC[6]
RSEFC[5]
RSEFC[4]
RSEFC[3]
RSEFC[2]
RSEFC[1]
RSEFC[0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Severely Errored 8-bit frame accumulation Counter
Note: A severely errored frame event is defined as the occurrence of
two consecutive errored frame alignment signals that are not
responsible for loss of frame alignment.
89
EXAR [ EXAR CORPORATION ]
