ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
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REV. 5.0.0
FIGURE 20. DATA BUS READ TIMING IN INTEL BUS MODE USING AS#
TASW
TASW
AS#
TAH1
TAH2
TAS1
TAS2
Valid
Address
Valid
Address
A0-A2
TCSH
TCSH
TCS2
TCS1
CS2#
TCS
TCS
CS0 or CS1
TRD1
TDY
TRD2
IOR#
IOR
TRD
TRD
TDIS
TDIS
DDIS#
D0-D7
TDD
TDD
TRDV
TRDV
Valid
Data
Valid
Data
Note: Only one chipselect and one read strobe should be used.
FIGURE 21. DATA BUS WRITE TIMING IN INTEL BUS MODE USING AS#
TASW
TASW
AS#
TAH1
TAH2
TAS1
TAS2
Valid
Address
Valid
Address
A0-A2
TCSH
TCSH
TCS1
TCS1
CS2#
TCS
TCS
CS0 or CS1
TDY
TWR1
TWR1
IOW#
IOW
TWR
TWR
TDS2
TDH2
TDS2
TDH2
Valid
Data
Valid
Data
D0-D7
Note: Only one chipselect and one write strobe should be used.
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