ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
áç
REV. 5.0.0
FIGURE 28. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED]
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
(Unloading)
T
S
S
S
S
T
D0:D7
T
S
D0:D7
T
D0:D7
T
D0:D7
T
D0:D7
S
D0:D7
T
ISR is read
TSI
IER[1]
enabled
ISR is read
TSRT
INT*
TX FIFO
Empty
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TWRI
Data in
TX FIFO
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TXDMA#
FIGURE 29. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED]
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX
(Unloading)
S
D0:D7
S
D0:D7
S
S
D0:D7
T
T
T
D0:D7
D0:D7
T
S
D0:D7
T
S D0:D7
T
IER[1]
enabled
ISR Read
ISR Read
TSI
TSRT
INT*
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TWRI
At least 1
empty location
in FIFO
TX FIFO
Full
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
TXDMA
48
EXAR [ EXAR CORPORATION ]
