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ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
REV. 5.0.0
FIGURE 26. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED]
Start
Bit
RX
S
S
S
S
S
T
S
D0:D7
D0:D7
D0:D7
T
D0:D7
TSSI
D0:D7
T
T
T
D0:D7
D0:D7
Stop
Bit
RX FIFO drops
below RX
Trigger Level
INT
TSSR
FIFO
Empties
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RXRDY#
First Byte is
Received in
RX FIFO
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
FIGURE 27. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED]
Start
Bit
Stop
Bit
RX
S
S
S
S
T
D0:D7
T
T
S
T
S
T
D0:D7
D0:D7
D0:D7
D0:D7
TSSI
D0:D7
D0:D7
RX FIFO drops
below RX
Trigger Level
INT
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
TSSR
FIFO
Empties
RXRDY#
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXFIFODMA
47
EXAR [ EXAR CORPORATION ]
