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ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
REV. 5.0.0
FIGURE 18. DATA BUS READ TIMING IN INTEL BUS MODE WITH AS# TIED TO GND
A0-
A2
Valid
Address
Valid
Address
TAS
TAS
TAH
TAH
CS2#
TCS
TCS
CS0
CS1
TDY
IOR#
IOR
TRD
TRD
TDD
TDD
TRDV
TRDV
Valid
Data
Valid
Data
D0-D7
Note: Only one chipselect and one read strobe should be used.
FIGURE 19. DATA BUS WRITE TIMING IN INTEL BUS MODE WITH AS# TIED TO GND
A0-
A2
Valid
Address
Valid
Address
TAS
TAS
TAH
TAH
CS2#
TCS
TCS
CS1
CS0
TDY
IOW#
IOW
TWR
TWR
TDH1
TDH1
TDS1
Valid
TDS1
Valid
D0-D7
Data
Data
Note: Only one chipselect and one write strobe should be used.
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