ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
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REV. 5.0.0
TABLE 13: UART RESET CONDITIONS
RESET STATE
REGISTERS
DLL
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
Bits 7-0 = 0x00
Bits 3-0 = logic 0
DLM
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
XFR
MSR
Bits 7-4 = logic levels of the inputs
IRPW
SPR
Bits 7-0 = 0x00
Bits 7-0 = 0xFF
EFR
Bits 7-0 = 0x00
XON1
XON2
XOFF1
XOFF2
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX
Normal = logic 1
Infrared = logic 0
RTS#
DTR#
Logic 1
Logic 1
Logic 1
Logic 1
Logic 0
Logic 1
OP1#
OP2#
TXRDY#
RXRDY#
INT (16 Mode)
INT# (68 Mode)
Logic 0
Logic 1
IRQA, IRQB, IRQC (PC Mode) Three-State Condition
38
EXAR [ EXAR CORPORATION ]
