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ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
REV. 5.0.0
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated (if IER bit-6 = 1) when the receive FIFO is filled to the programmed
trigger level and RTS de-asserts to a logic 1 at the next upper trigger level. RTS# will return to a logic 0 when
FIFO data falls below the next lower trigger level. The RTS# output must be asserted (logic 0) before the auto
RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is
disabled.
• Logic 0 = Automatic RTS flow control is disabled. (default)
• Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
• Logic 0 = Automatic CTS flow control is disabled. (default)
• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# input returns to a logic 0.
4.17 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 5.
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EXAR [ EXAR CORPORATION ]
