6.9 Power and Ground Pins
Table 6-25. Power and Ground pins (Sheet 1 of 2)
Signal Name
vdde
I/O Type
Power
Description
3.3V External I/O power (includes RMII VDD)
I/O VDD for Host GMII (3.3V) or RGMII (1.5V or 2.5V)
vddh
Power
If both host and network ports are configured for SERDES/
SGMII, it is acceptable to connect vddn and vddh to 3.3V.
This may save some PCB real estate and reduce the
component cost/count because a dedicated 2.5V power
supply not required.
vddi
Power
Power
1.0V Internal Core Logic Power
vddn
I/O VDD for Network RGMII (1.5V or 2.5V) Interface.
If both host and network ports are configured for SERDES/
SGMII, it is acceptable to connect vddn and vddh to 3.3V.
This may save some PCB real estate and reduce the
component cost/count because a dedicated 2.5V power
supply not required.
vddr
Power
Power
Input
DDR I/O power 1.8V (DDR2)
SERDES VDD 1.0V
vdds
vdd_reserved
3.3V Reference Voltage for PLL. This is a test pin used
during the manufacturing process.
vss
Ground
Input
Ground for Core logic and I/O
vref[_ddr[2:0]
DDR Voltage Reference for SSTL bi-directional I/O
0.9V for DDR2
vref_netw
vref_host
Input
Input
Input
0.75V Network Side GMACs Reference Voltage
Should be tied to Ground if the 1.5V RGMII interface
option is NOT used.
0.75V Host Side GMACs Reference Voltage
Should be tied to Ground if the 1.5V RGMII interface
option is NOT used.
vttn_serdes
SERDES Network driver termination voltage (A/B)
Variable depending on the Application
vttn_serdes (V)
VSW (ac, mV)
1.0
1.2
1.5
1.8
250
350
500
750
Provides a method for varying the voltage swing on the
Network side SERDES differential ouputs. 1V p-p
differential signaling is common, vttn_serdes is normally
tied to 1.5 V.
4450 – Data Sheet, DS-0131-06
Page62
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