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16C2850 参数 Datasheet PDF下载

16C2850图片预览
型号: 16C2850
PDF下载: 下载PDF文件 查看货源
内容描述: 双UART,具有128字节FIFO的和RS- 485半双工控制 [DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL]
分类和应用: 先进先出芯片
文件页数/大小: 44 页 / 670 K
品牌: EXAR [ EXAR CORPORATION ]
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XR16C2850  
Table 3, INTERNAL REGISTER DECODE  
A2  
A1  
A0  
READ MODE  
WRITE MODE  
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Holding Register  
Interrupt Status Register  
Transmit Holding Register  
Interrupt Enable Register  
FIFO Control Register  
Line Control Register  
Modem Control Register  
Line Status Register  
Modem Status Register  
Scratchpad Register  
Scratchpad Register  
Baud Rate Register Set (DLL/DLM): Note *3  
0
0
0
0
0
1
LSB of Divisor Latch  
MSB of Divisor Latch  
LSB of Divisor Latch  
MSB of Divisor Latch  
Enhanced Register Set (EFR, Xon/off 1-2): Note *4  
0
0
0
1
1
1
1
1
0
0
1
0
0
1
1
1
0
1
0
0
1
0
1
1
FIFO Trigger Register  
FIFO trigger counter  
Feature Control Register  
Enhanced Feature Register  
Xon-1 Word  
Xon-2 Word  
Xoff-1 Word  
Enhanced Feature Register  
Xon-1 Word  
Xon-2 Word  
Xoff-1 Word  
Xoff-2 Word  
Xoff-2 Word  
Enhanced Mode Select Register  
Note *3: These registers are accessible only when LCR bit-7 is set to a logic 1.  
Note *4: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when the LCR is set to “BF” (HEX).  
Rev. 1.00P  
9
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