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16C2850 参数 Datasheet PDF下载

16C2850图片预览
型号: 16C2850
PDF下载: 下载PDF文件 查看货源
内容描述: 双UART,具有128字节FIFO的和RS- 485半双工控制 [DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL]
分类和应用: 先进先出芯片
文件页数/大小: 44 页 / 670 K
品牌: EXAR [ EXAR CORPORATION ]
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XR16C2850  
FIFO Operation  
Hardware Flow Control  
The 128 byte transmit and receive data FIFO are  
enabled by the FIFO Control Register (FCR) bit-0.  
With 16C2550 devices, the user can set the receive  
trigger level but not the transmit trigger level. The  
2850 provides independent trigger levels for both  
receiver and transmitter. To remain compatible with  
ST16C2550, the transmit interrupt trigger level is set  
to 16 following a reset. It should be noted that the user  
cansetthetransmittriggerlevelsbywritingtotheFCR  
register, but activation will not take place until EFR bit-  
4issettoalogic1. ThereceiverFIFOsectionincludes  
a time-out function to ensure data is delivered to the  
external CPU. An interrupt is generated whenever the  
Receive Holding Register (RHR) has not been read  
following the loading of a character or the receive  
triggerlevelhasnotbeenreached. (seehardwareflow  
control for a description of this timing).  
When automatic hardware flow control is enabled, the  
2850 monitors the -CTS pin for a remote buffer  
overflow indication and controls the -RTS pin for local  
buffer overflows. Automatic hardware flow control is  
selected by setting bits 6 (RTS) and 7 (CTS) of the  
EFR register to a logic 1. If -CTS transitions from a  
logic0toalogic1indicatingaflowcontrolrequest,ISR  
bit-5 will be set to a logic 1 (if enabled via IER bit 6-7),  
and the 2850 will suspend TX transmissions as soon  
asthestopbitofthecharacterinprocessisshiftedout.  
Transmission is resumed after the -CTS input returns  
to a logic 0, indicating more data may be sent.  
With the Auto RTS function enabled, an interrupt is  
generated when the receive FIFO reaches the pro-  
grammed trigger level. The -RTS pin will not be forced  
to a logic 1 (RTS Off), until the receive FIFO reaches  
the next trigger level. The-RTSpinwillreturntoalogic  
0 after the data buffer (FIFO) is unloaded to the next  
trigger level below the programmed trigger level.  
Under the above described conditions the 2850 will  
continue to accept data until the receive FIFO is full.  
Example of 650 trigger level selection  
Selected  
Trigger  
INT  
Pin  
-RTS  
Logic “1”  
-RTS  
Logic “0”  
Level  
Activation  
(characters) (characters)  
(characters)  
8
8
16  
24  
28  
28  
0
8
16  
24  
16  
24  
28  
16  
24  
28  
Rev. 1.00P  
10  
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