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16C2850 参数 Datasheet PDF下载

16C2850图片预览
型号: 16C2850
PDF下载: 下载PDF文件 查看货源
内容描述: 双UART,具有128字节FIFO的和RS- 485半双工控制 [DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL]
分类和应用: 先进先出芯片
文件页数/大小: 44 页 / 670 K
品牌: EXAR [ EXAR CORPORATION ]
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XR16C2850  
SYMBOL DESCRIPTION  
Symbol  
Pin  
44  
Signal  
type  
Pin Description  
40  
48  
-OP2 A-B  
31,13 35,15 32,9  
O
Output -2 (User Defined) - This function is associated with  
individual channels, A through B. The state at these pin(s)  
are defined by the user and through the software setting of  
MCR register bit-3. INT A-B are set to the active mode and  
OP2 to a logic 0 when MCR-3 is set to a logic 1. INT A-B are  
set to the three state mode and OP2 to a logic 1 when MCR-  
3 is set to a logic 0. See bit-3, Modem Control Register  
(MCR bit-3).  
RESET  
35  
39  
36  
I
Reset (active high) - A logic 1 on this pin will reset the  
internal registers and all the outputs. The UART transmitter  
output and the receiver input will be disabled during reset  
time (see XR16C2850 External Reset Conditions for initial-  
ization details).  
-RXRDY A-B  
-
34,23 31,18  
O
Receive Ready A-B (active low) - This function is associ-  
atedwith44pinPLCCand48pinTQFPpackagesonly.This  
function provides the RX FIFO/RHR status for individual  
receive channels (A-B). RXRDY is primarily intended for  
monitoring DMA mode 1 transfers for the receive data  
FIFO’s. A logic 0 indicates there is receive data to read/  
unload, i.e., receive ready status with one or more RX  
characters available in the FIFO/RHR. This pin is a logic 1  
when the FIFO/RHR is empty or when the programmed  
trigger level has not been reached. This signal can also be  
used for single mode transfers (DMA mode 0).  
-TXRDY A-B  
-
1,12  
43,6  
O
Transmit Ready A-B (active low) - This function is associ-  
ated with 44 pin PLCC and 48 pin TQFP packages only.  
These outputs provide the TX FIFO/THR status for indi-  
vidual transmit channels (A-B). TXRDY is primarily in-  
tended for monitoring DMA mode 1 transfers for the trans-  
mit data FIFO’s. An individual channel’s -TXRDY A-B buffer  
ready status is indicated by logic 0, i.e., at least one location  
is empty and available in the FIFO or THR. This pin goes to  
a logic 1 when there are no more empty locations in the  
FIFO or THR. This signal can also be used for single mode  
transfers (DMA mode 0).  
VCC  
40  
44  
42  
Pwr  
Power supply input.  
Rev. 1.00P  
5
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