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16C2850 参数 Datasheet PDF下载

16C2850图片预览
型号: 16C2850
PDF下载: 下载PDF文件 查看货源
内容描述: 双UART,具有128字节FIFO的和RS- 485半双工控制 [DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL]
分类和应用: 先进先出芯片
文件页数/大小: 44 页 / 670 K
品牌: EXAR [ EXAR CORPORATION ]
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XR16C2850  
Software Flow Control  
normal incoming RX data. This condition is selected in  
conjunction with EFR bits 0-3. Note that software flow  
control should be turned off when using this special  
mode by setting EFR bit 0-3 to a logic 0.  
When software flow control is enabled, the 2850  
compares one or two sequential receive data charac-  
ters with the programmed Xon or Xoff-1,2 character  
value(s). If receive character(s) (RX) match the pro-  
grammed values, the 2850 will halt transmission (TX)  
as soon as the current character(s) has completed  
transmission. When a match occurs, the receive  
ready (if enabled via Xoff IER bit-5) flags will be set  
and the interrupt output pin (if receive interrupt is  
enabled) will be activated. Following a suspension  
due to a match of the Xoff characters values, the 2850  
will monitor the receive data stream for a match to the  
Xon-1,2 character value(s). If a match is found, the  
2850 will resume operation and clear the flags (ISR  
bit-4).  
The 2850 compares each incoming receive character  
with Xoff-2 data. If a match exists, the received data  
will be transferred to FIFO and ISR bit-4 will be set to  
indicate detection of special character (see Figure 9).  
Although the Internal Register Table shows each X-  
Register with eight bits of character information, the  
actual number of bits is dependent on the pro-  
grammed word length. Line Control Register (LCR)  
bits 0-1 defines the number of character bits, i.e.,  
either 5 bits, 6 bits, 7 bits, or 8 bits. The word length  
selected by LCR bits 0-1 also determines the number  
of bits that will be used for the special character  
comparison. Bit-0 in the X-registers corresponds with  
the LSB bit for the receive character.  
Reset initially sets the contents of the Xon/Xoff 8-bit  
flow control registers to a logic 0. Following reset the  
user can write any Xon/Xoff value desired for software  
flow control. Different conditions can be set to detect  
Xon/Xoff characters and suspend/resume transmis-  
sions. When double 8-bit Xon/Xoff characters are  
selected, the 2850 compares two consecutive receive  
characters with two software flow control 8-bit values  
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmis-  
sions accordingly. Under the above described flow  
control mechanisms, flow control characters are not  
placed (stacked) in the user accessible RX data buffer  
or FIFO.  
Time-out Interrupts  
Three special interrupts have been added to monitor  
the hardware and software flow control. The interrupts  
are enabled by IER bits 5-7. Care must be taken when  
handling these interrupts. Following a reset the trans-  
mitter interrupt is enabled, the 2850 will issue an  
interrupt to indicate that transmit holding register is  
empty. This interrupt must be serviced prior to con-  
tinuing operations. The LSR register provides the  
current singular highest priority interrupt only. It could  
be noted that CTS and RTS interrupts have lowest  
interrupt priority. A condition can exist where a higher  
priority interrupt may mask the lower priority CTS/  
RTS interrupt(s). Only after servicing the higher pend-  
ing interrupt will the lower priority CTS/ RTS  
interrupt(s) be reflected in the status register. Servic-  
ing the interrupt without investigating further interrupt  
conditions can result in data errors.  
In the event that the receive buffer is overfilling and  
flow control needs to be executed, the 2850 automati-  
cally sends an Xoff message (when enabled) via the  
serial TX output to the remote modem. The 2850  
sends the Xoff-1,2 characters as soon as received  
data passes the programmed trigger level. To clear  
this condition, the 2850 will transmit the programmed  
Xon-1,2 characters as soon as receive data drops  
below the programmed trigger level.  
When two interrupt conditions have the same priority,  
it is important to service these interrupts correctly.  
Receive Data Ready and Receive Time Out have the  
same interrupt priority (when enabled by IER bit-0).  
The receiver issues an interrupt after the number of  
characters have reached the programmed trigger  
level. In this case the 2850 FIFO may hold more  
characters than the programmed trigger level. Follow-  
Special Feature Software Flow Control  
A special feature is provided to detect an 8-bit charac-  
ter when bit-5 is set in the Enhanced Feature Register  
(EFR). When this character is detected, it will be  
placed on the user accessible data stack along with  
Rev. 1.00P  
11  
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