EMD3D256M08BS1
EMD3D256M16BS1
Burst Length, Type and Order
Accesses within a given burst may be programmed only in a sequential order which is selected via bit A3
of Mode Register MR0=0. The ordering of accesses within a burst is determined by the burst length and the
starting column address as shown in Table 14 below. The burst length is defined by bits A1:A0 of Mode Reg-
ister MR0. Burst length options include fixed BC4, fixed BL8, and “on the fly”which allows BC4 or BL8 to be
selected coincident with the registration of a Read or Write command via A12/BC_n.
Table 14 – Burst Length, Type and Order
Burst
Length
READ/
WRITE
Starting Column Address
A[2,1,0]
Burst Type = Sequencial
(Decimal)
000
100
0, 1, 2, 3, T, T, T, T
4, 5, 6, 7, T, T, T, T
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
4, 5, 6, 7, 0, 1, 2, 3
0, 1, 2, 3, 4, 5, 6, 7
READ
BC4
BL8
0, V, V
1, V, V
000
WRITE
READ
100
WRITE
V, V, V
Burst Type/Burst Order supports only the sequential burst type for CA<2:0 = 000 or 100
EMD3D256M08BS1/16BS1 Revision 1.3 10/2018
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