EtronTech
EM68C16CWQG
Table 14. Precharge & Auto Precharge Clariification
Minimum Delay between “From
Command” to “To Command”
From Command
Read
To Command
Unit Note
tCK 1,2
tCK 1,2
Precharge (to same Bank as Read)
Precharge All
Precharge (to same Bank as Read w/AP)
Precharge All
Precharge (to same Bank as Write)
Precharge All
Precharge (to same Bank as Write w/AP)
Precharge All
AL+BL/2+max(RTP,2)-2
AL+BL/2+max(RTP,2)-2
AL+BL/2+max(RTP,2)-2
AL+BL/2+max(RTP,2)-2
Read w/AP
Write
WL+BL/2+tWR
WL+BL/2+tWR
WL+BL/2+tWR
WL+BL/2+tWR
tCK
tCK
tCK
tCK
2
2
2
2
Write w/AP
Precharge
Precharge All
Precharge (to same Bank as Precharge)
Precharge All
1
1
1
1
Precharge
Precharge All
NOTE 1: RTP [cycles] =RU {tRTP [ns]/tCK (avg) [ns]}, where RU stands for round up.
NOTE 2: For a given bank, the precharge period should be counted from the latest precharge command, either
one bank precharge or precharge all, issued to that bank.The prechrage period is satisfied after tRP or tRPall(=tRP
for 8 bank device + 1X tCK) depending on the latest precharge command issued to that bank.
Refresh command
When CS#, RAS# and CAS# are held LOW and WE# HIGH at the rising edge of the clock, the chip enters the
Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Precharge
time (tRP) before the Refresh command (REF) can be applied. An address counter, internal to the device, supplies
the bank address during the refresh cycle. No control of the external address bus is required once this cycle has
started.
When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A delay
between the Refresh command (REF) and the next Activate command or subsequent Refresh command must be
greater than or equal to the Refresh cycle time (tRFC).To allow for improved efficiency in scheduling and switching
between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Refresh commands
can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh
command and the next Refresh command is 9 * tREFI
.
Self refresh operation
The Self Refresh command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is
powered down. When in the Self Refresh mode, the DDR2 SDRAM retains data without external clocking. The
DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is
defined by having CS#, RAS#, CAS# and CKE# held LOW with WE# HIGH at the rising edge of the clock. ODT
must be turned off before issuing Self Refresh command, by either driving ODT pin LOW or using EMRS command.
Once the Command is registered, CKE must be held LOW to keep the device in Self Refresh mode. The DLL is
automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the
DDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are “don‟t care”. For proper
Self Refresh operation all power supply pins (VDD, VDDQ, VDDL and VREF) must be at valid levels. The DRAM initiates a
minimum of one refresh command internally within tCKE period once it enters Self Refresh mode. The clock is
internally disabled during Self Refresh Operation to save power. The minimum time that the DDR2 SDRAM must
remain in Self Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock
one clock after Self Refresh entry is registered, however, the clock must be restarted and stable before the device
can exit Self Refresh operation.
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to
CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least tXSNR must be satisfied before a valid
command can be issued to the device to allow for any internal refresh in progress. CKE must remain HIGH for the
entire Self Refresh exit period tXSRD for proper operation except for Self Refresh re-entry. Upon exit from Self
Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after waiting at least tXSNR period and issuing
one refresh command(refresh period of tRFC). NOP or Deselect commands must be registered on each positive clock
edge during the Self Refresh exit interval tXSNR. ODT should be turned off during tXSRD. The use of Self Refresh mode
introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self
Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto refresh
command before it is put back into Self Refresh mode.
Rev. 1.2
20
Apr. /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
