EtronTech
EM68C16CWQG
Auto precharge operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge
Command or the auto-precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the
CAS# timing accepts one extra address, column address A10, to allow the active bank to automatically begin
precharge at the earliest possible moment during the burst read or write cycle. If A10 is LOW when the READ or
WRITE Command is issued, then normal Read or Write burst operation is executed and the bank remains active at
the completion of the burst sequence. If A10 is HIGH when the Read or Write Command is issued, then the auto-
precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception
that the active bank will begin to precharge on the rising edge which is CAS latency (CL) clock cycles before the end
of the read burst. Auto-precharge also be implemented during Write commands. The precharge operation engaged
by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the
memory array. This feature allows the precharge operation to be partially or completely hidden during burst Read
cycles (dependent upon CAS latency) thus improving system performance for random data access. The RAS#
lockout circuit internally delays the Precharge operation until the array restore operation has been completed (tRAS
satisfied) so that the auto precharge command may be issued with any Read or Write command.
Burst read with auto precharge
If A10 is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2
SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with
AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-
Precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start point
of Auto-precharge operation will be delayed until tRTP(min) is satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not
at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the
next Activate command becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to the next
Activate command is AL + 2 + tRTP + tRP. Note that both parameters tRTP and tRP have to be rounded up to the next
integer value. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
A new bank active (command) may be issued to the same bank if the following two conditions are satisfied
simultaneously:
(1) The RAS# precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins.
(2) The RAS# cycle time (tRC) from the previous bank activation has been satisfied.
Burst write with auto precharge
If A10 is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2
SDRAM automatically begins precharge operation after the completion of the burst write plus Write recovery time
(tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following
two conditions are satisfied.
(1) The data-in to bank activate delay time (WR + tRP) has been satisfied.
(2) The RAS# cycle time (tRC) from the previous bank activation has been satisfied.
Rev. 1.2
19
Apr. /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
