EtronTech
EM68C16CWQG
Write data mask
One Write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the
implementation on DDR SDRAMs. It has identical timings on Write operations as the data bits, and though used
in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not
used during read cycles.
Precharge operation
The Precharge command is used to precharge or close a bank that has been activated. The Precharge Command is
triggered when CS#, RAS# and WE# are LOW and CAS# is HIGH at the rising edge of the clock. The Precharge
Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10,
BA2, BA1, and BA0 are used to define which bank to precharge when the command is issued.
Table 13. Bank Selection for Precharge by address bits
A10
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
BA2
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
BA1
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
BA0
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
Precharged Bank(s)
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
Bank 4 only
Bank 5 only
Bank 6 only
Bank 7 only
ALL Banks
DON‟T CARE DON‟T CARE DON‟T CARE
Burst read operation followed by precharge
Minimum Read to precharge command spacing to the same bank = AL + BL/2 + max (RTP, 2) - 2 clocks. For the
earliest possible precharge, the precharge command may be issued on the rising edge which “Additive latency (AL)
+ BL/2 clocks” after a Read command. A new bank active (command) may be issued to the same bank after the
RAS# precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that
initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For
BL = 4 this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8 this is
the time from AL + 2 clocks after the Read to the Precharge command.
Burst Write operation followed by precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay must
be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay
is known as a write recovery time (tWR) referenced from the completion of the burst write to the Precharge command.
No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not support any burst
interrupt by a Precharge command. tWR is an analog timing parameter and is not the programmed value for tWR in the
MRS.
Rev. 1.2
18
Apr. /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
