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EM68B16DVAA-6H 参数 Datasheet PDF下载

EM68B16DVAA-6H图片预览
型号: EM68B16DVAA-6H
PDF下载: 下载PDF文件 查看货源
内容描述: 32M ×16的移动DDR同步DRAM ( SDRAM ) [32M x 16 Mobile DDR Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 40 页 / 323 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM68B16DVAA  
EtronTech  
Write Interrupted by Write  
A Burst Write can be interrupted by the new Write command before completion of the previous Burst Write,  
with the only restriction being that the interval that separates the commands must be at least one clock cycle.  
When the previous burst is interrupted, the remaining addresses are overridden by the new addresses and  
the new data will be written into the device until the programmed Burst Length is satisfied.  
Write Interrupted by Read & DM  
A Burst Write can be interrupted by a Read command to any bank. The DQ must be in the high impedance  
state at least one clock cycle before the interrupting read data appears on the outputs to avoid data  
contention. When the Read command is to be asserted, any residual data from the Burst Write sequence  
must be masked by DM. The delay from the last data to the Read command (tWTR) is required to avoid data  
contention inside the DRAM. Data presented on the DQ pins before the Read command is initiated will  
actually be written to the memory. A Read command interrupting a write sequence can not be issued at the  
next clock edge following the Write command.  
Write Interrupted by Precharge & DM  
A Burst Write can be interrupted by a Precharge of the same bank before completion of the previous burst. A  
write recovery time (tWR) is required from the last data to the Precharge command. When the Precharge  
command is asserted, any residual data from the Burst Write cycle must be masked by DM.  
z Burst Stop Command  
The Burst Stop command is initiated by having  
and  
High with  
and  
Low at the rising  
WE  
RAS  
CAS  
CS  
edge of the clock only. The Burst Stop command has the fewest restrictions, making it the easiest method to  
use when terminating a burst operation before it has been completed. When the Burst Stop command is  
issued during a Burst Read cycle, both the data and DQS (Data Strobe) go to a high impedance state after a  
delay which is equal to the  
latency set in the Mode Register. The Burst Stop command, however, is not  
CAS  
supported during a Burst Write operation.  
z DM Masking Function  
The DDR SDRAM has a Data Mask function that can be used in conjunction with the data write cycle only,  
not the read cycle. When the Data Mask is activated (DM High) during a write operation, the write data is  
masked immediately (DM to Data Mask latency is zero). DM must be issued at the rising edge or the falling  
edge of Data Strobe instead of at a clock edge.  
z Auto Precharge Operation  
Auto Precharge is a feature which performs the same individual bank precharge function as described above,  
but without requiring an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto  
Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank / row that is  
addressed with the READ or WRITE command is automatically performed upon completion of the read or  
write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each individual READ  
or WRITE command. Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a  
burst. The user must not issue another command to the same bank until the precharging time (tRP) is  
completed. When the Auto Precharge command is activated, the active bank automatically begins to  
precharge at the earliest possible moment during a read or write cycle after tRAS (min) is satisfied.  
z Precharge Command  
The Precharge command is issued when  
,
, and  
are Low and  
is High at the rising edge  
CAS  
CS RAS  
WE  
of the clock (CK). The Precharge command can be used to precharge any bank individually or all banks  
simultaneously. The Bank Select addresses (BA0, BA1) are used to define which bank is precharged when  
the command is initiated. For a write cycle, tWR (min) must be satisfied from the start of the last Burst Write  
cycle until the Precharge command can be issued. After tRP from the precharge, an Active command to the  
same bank can be initiated.  
Etron Confidential  
11  
Rev. 1.0  
Mar. 2009  
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