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EM68B16DVAA-6H 参数 Datasheet PDF下载

EM68B16DVAA-6H图片预览
型号: EM68B16DVAA-6H
PDF下载: 下载PDF文件 查看货源
内容描述: 32M ×16的移动DDR同步DRAM ( SDRAM ) [32M x 16 Mobile DDR Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 40 页 / 323 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM68B16DVAA  
EtronTech  
Table 12. Electrical AC Characteristics  
(VDD=1.7V~1.95V, TA =-25~85°C)  
-6  
-75  
Symbol  
Parameter  
Unit Note  
Min.  
12  
Max.  
-
Min.  
12  
Max.  
-
CL = 2  
CL = 3  
1
ns  
Clock cycle time  
tCK  
6
100  
0.55  
0.55  
7.5  
100  
0.55  
0.55  
1
ns  
Clock high level width  
Clock low level width  
0.45  
0.45  
0.45  
0.45  
tCH  
tCK  
tCK  
ns  
tCL  
2
2
5.5  
5.5  
2
2
6
6
DQS-out access time from CK,  
tDQSCK  
CK  
CK  
2
Output access time from CK,  
tAC  
ns  
DQS-DQ Skew  
-
0.5  
1.1  
0.6  
1.25  
-
-
0.6  
1.1  
0.6  
1.25  
-
tDQSQ  
tRPRE  
tRPST  
tDQSS  
tWPRES  
tWPRE  
tWPST  
tDQSH  
tDQSL  
ns  
tCK  
tCK  
tCK  
Read preamble  
0.9  
0.4  
0.75  
0
0.9  
0.4  
0.75  
0
Read postamble  
CK to valid DQS-in  
DQS-in setup time  
3
ns  
DQS write preamble  
DQS write postamble  
DQS in high level pulse width  
DQS in low level pulse width  
0.25  
0.4  
0.4  
0.4  
-
0.25  
0.4  
0.4  
0.4  
-
tCK  
tCK  
tCK  
tCK  
0.6  
0.6  
0.6  
0.6  
0.6  
0.6  
Address and Control input setup time  
Address and Control input hold time  
DQ & DM setup time to DQS  
1.1  
1.1  
0.6  
0.6  
-
-
-
-
1.3  
1.3  
0.8  
0.8  
-
-
-
-
1
tIS  
ns  
1
tIH  
ns  
4, 5  
tDS  
tDH  
ns  
DQ & DM hold time to DQS  
4, 5  
ns  
tCLMIN or  
tCHMIN  
tCLMIN or  
tCHMIN  
Clock half period  
-
-
tHP  
ns  
Output DQS valid window  
Row cycle time  
-
-
tQH  
tHP – 0.65  
tHP – 0.75  
67.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
60  
110  
42  
-
-
-
-
tRC  
Refresh row cycle time  
Row active time  
110  
tRFC  
tRAS  
tRCD  
100K  
45  
100K  
18  
-
22.5  
-
to  
RAS CAS  
Delay for Read or Write  
Row precharge time  
18  
-
22.5  
-
tRP  
Row active to Row active delay  
Write recovery time  
12  
-
15  
-
tRRD  
twR  
12  
-
15  
-
8
ns  
Auto precharge write recovery + Precharge  
Internal Write to Read Delay  
tWR+tRP  
-
tWR+tRP  
-
tDAL  
tWTR  
tCCD  
tMRD  
tXSR  
tXP  
tCK  
2
1
-
1
1
-
7
tCK  
Col. Address to Col. Address delay  
Mode register set cycle time  
-
-
tCK  
tCK  
ns  
2
-
-
2
-
-
Self refresh exit to next valid command delay  
200  
25  
-
200  
25  
-
Exit Power Down mode to first valid command  
Refresh interval time  
-
-
6
ns  
7.8  
7.8  
tREFI  
Note:  
µs  
1. Table 13.Input Setup / Hold Slew Rate Derating  
Input Setup/Hold Slew Rate (V/ns)  
tIH (ps)  
tIS (ps)  
1.0  
0.8  
0.6  
0
0
+50  
+50  
+100  
+100  
This derating table is used to increase tIS / tIH in the case where the input slew rate is below 1.0V/ns.  
Etron Confidential  
15  
Rev. 1.0  
Mar. 2009