EM68B16DVAA
EtronTech
z Mode Register Set(MRS)
The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs
Latency, Burst Type, and Burst Length to make the Mobile DDR SDRAM useful for a variety of
CAS
applications. The default value of the Mode Register is not defined; therefore the Mode Register must be
written by the user. Values stored in the register will be retained until the register is reprogrammed, the device
enters Deep Power Down mode, or power is removed from the device. The Mode Register is written by
asserting Low on
,
,
,
, BA1 and BA0 (the device should have all banks idle with no bursts
CS RAS CAS WE
in progress prior to writing into the mode register, and CKE should be High). The state of address pins
A0~A12 and BA0, BA1 in the same cycle in which and are asserted Low is written into
,
,
CS RAS CAS
WE
the Mode Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the
Mode Register. The Mode Register is divided into various fields depending on functionality. The Burst Length
uses A0~A2, Burst Type uses A3, and
Latency (read latency from column address) uses A4~A6. A logic
CAS
0 should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should
not be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for
specific codes for various burst lengths, burst types and
latencies.
CAS
Table 4. Mode Register Bitmap
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0
0
0
0
0
0
BT Burst Length Mode Register
CAS Latency
A6 A5 A4
A2 A1 A0 Burst Length
Latency A3 Burst Type
CAS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
0 Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
1
2
2
4
3
8
Reserved
Reserved
Reserved
Reserved
16
Reserved
Reserved
Reserved
CK
CK
PRE
ALL
Any
Command
NOP
NOP
NOP
MRS*1
NOP
NOP
NOP
Command
*2
tMRD= 2*tCK
tRP
*1: MRS can be issued only with all banks in the idle state.
*2: A minimum delay of tRP is required before issuing an MRS command.
Don’t Care
Figure 3.Mode Register Set Cycle
Etron Confidential
7
Rev. 1.0
Mar. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
