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EM68B16DVAA-6H 参数 Datasheet PDF下载

EM68B16DVAA-6H图片预览
型号: EM68B16DVAA-6H
PDF下载: 下载PDF文件 查看货源
内容描述: 32M ×16的移动DDR同步DRAM ( SDRAM ) [32M x 16 Mobile DDR Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 40 页 / 323 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM68B16DVAA  
EtronTech  
Table 11. D.C. Characteristics  
(VDD=1.7V~1.95V, TA =-25~85°C)  
-6  
-75  
Parameter & Test Condition  
Symbol  
Unit  
MAX  
Operating one bank active-precharge current:  
IDD0  
70  
0.3  
0.3  
15  
8
65  
0.3  
0.3  
15  
8
mA  
tRC=tRC(min); tCK=tCK(min); CKE is HIGH; CS is HIGH between valid  
commands; Address inputs are SWITCHING; data bus inputs are STABLE  
Precharge power-down standby current:  
IDD2P  
IDD2PS  
IDD2N  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
All banks idle, CKE is LOW; CS is HIGH, tCK=tCK(min);  
address and control inputs are SWITCHING; data bus inputs are STABLE  
Precharge power-down standby current with clock stop:  
All banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;  
address and control inputs are SWITCHING; data bus inputs are STABLE  
Precharge non power-down standby current:  
All banks idle, CKE is HIGH; CS is HIGH, tCK=tCK(min);  
address and control inputs are SWITCHING; data bus inputs are STABLE  
Precharge non power-down standby current with clock stop:  
IDD2NS  
IDD3P  
All banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;  
address and control inputs are SWITCHING; data bus inputs are STABLE  
Active power-down standby current:  
0.5  
0.5  
15  
10  
0.5  
0.5  
15  
10  
One bank active, CKE is LOW; CS is HIGH, tCK=tCK(min);  
address and control inputs are SWITCHING; data bus inputs are STABLE  
Active power-down standby current with clock stop:  
IDD3PS  
IDD3N  
One bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;  
address and control inputs are SWITCHING; data bus inputs are STABLE  
Active non power-down standby current:  
One bank active, CKE is HIGH; CS is HIGH, tCK=tCK(min) address and  
control inputs are SWITCHING; data bus inputs are STABLE  
Active non power-down standby current with clock stop:  
IDD3NS  
One bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;  
address and control inputs are SWITCHING; data bus inputs are STABLE  
Operating burst read current:  
One bank active; BL = 4; CL = 3; tCK=tCK(min); continuous read bursts; IOUT  
0 mA address inputs are SWITCHING; 50% data change each burst transfer  
Operating burst write current:  
One bank active; BL = 4; tCK=tCK(min); continuous write bursts;  
address inputs are SWITCHING; 50% data change each burst transfer  
Auto-Refresh current:  
=
IDD4R  
IDD4W  
IDD5  
110  
100  
90  
100  
90  
mA  
mA  
mA  
tRC = tRFC(min); tCK=tCK(min); burst refresh; CKE is HIGH;  
90  
address and control inputs are SWITCHING; data bus inputs are STABLE  
Self refresh current:  
µA  
µA  
µA  
µA  
TCSR Range  
Max.40 Max.85  
CKE is LOW, CK = LOW, CK = HIGH; Extended Mode  
Full Array  
Register set to all address and control inputs are STABLE;  
data bus inputs are STABLE  
490  
350  
280  
700  
460  
340  
IDD6  
IDD8  
1/2 Full Array  
1/4 Full Array  
10  
Deep Power Down Mode Current  
Note:  
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the  
device.  
2. All voltages are referenced to VSS.  
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the  
minimum value of tCK and tRC. Input signals are changed one time per two clock cycles.  
Etron Confidential  
14  
Rev. 1.0  
Mar. 2009  
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