Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
T22
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
RAx
RAx
RAx
A10
CAy
CBx
CBy
CAy
CBz
RAx
CBw
A0~A11
DQM
tRCD
tAC2
Hi-Z
Bz2 Bz3
Bz1
Ax0
Ax1 Ax2
Ax3
By0
Ay1
DQ
Bw0
Bw1
Bx0 Bx1
By1 Ay0
Bz0
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command Command
Bank B Bank B
Read
Read
Command
Bank A
Read
Precharge
Command
Bank B
Read
Command
Bank B
Command
Bank B
Precharge
Comm and
Bank A
Preliminary
45
Rev 0.6
Sep. 2003
ETRON [ ETRON TECHNOLOGY, INC. ]
