Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 12.2. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAy
RBx
RAx
RAy
CAy
RBx
RAx
CAx
CBx
A0~A11
DQM
tRCD
tWR*
tRP
tWR*
Hi-Z
DQ
DBx7
DAx7 DBx0 DBx1 DBx2 DBx3 DBx4DBx5 DBx6
DAy3
DAy4
DAx6
DAy0DAy1DAy2
DAx0 DAx1 DAx2 DAx3 DAx4DAx5
Activate
Write
Activate
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank A
Write
Command Command
Bank A Bank A
Command
Bank A
Precharge
Precharge
Command
Bank B
Command
Bank A
*
tWR > tWR(min.)
Preliminary
41
Rev 0.6
Sep. 2003
ETRON [ ETRON TECHNOLOGY, INC. ]
