Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx
RBw
RBw
CBw
CBx
CBy
CBz
CAx
CAy
A0~A11
DQM
tWR
tRCD
tRP
tRP
tRRD
Hi-Z
DQ
DAx0
DAx1 DAx2 DAx3DBw0 DBw1DBx0
DBz2
DBx1DBy0
DBy1DAy0 DAy1 DBz0 DBz1
DBz3
Activate
Command Comm and
Bank A Bank A
Write
Activate
Comm and
Bank B
Write
Comm and Command
Bank B Bank B
Write
Write
Command Command
Bank B Bank A
Write
Write
Command
Bank B
Precharge
Command
Bank B
Precharge
Command
Bank A
Preliminary
48
Rev 0.6
Sep. 2003