Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 14.2. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx
RBx
CAx RBx
CBx
CBz
CBy
CAy
A0~A11
DQM
tAC3
tRCD
Hi-Z
DQ
Bx0
Bx1
By0 By1
Bz1 Ay0
Ay2
Ax0
Ax1 Ax2
Ax3
Bz0
Ay1
Ay3
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read Prechaerge
CommanCdommand
Bank A Bank B
Activate
Command
Bank B
Preliminary
46
Rev 0.6
Sep. 2003