Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx
CAx
CAz
CAy
A0~A11
DQM
Hi-Z
Az3
DQ
Ax0
Ax1
Ax2 Ax3
DAy0 DAy1
DAy3
Az0 Az1
Activate
Read
Write
The Write Data
Read
Comm and
Bank A
The Read Data
Command Comm and
Comm and is Maskedwith a
is Maskedwith a
Two Clock
Bank A
Bank A
Bank A
Zero Clock
Latency
Latency
Preliminary
44
Rev 0.6
Sep. 2003