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EM636165-XXI 参数 Datasheet PDF下载

EM636165-XXI图片预览
型号: EM636165-XXI
PDF下载: 下载PDF文件 查看货源
内容描述: 1Mega ×16同步DRAM (SDRAM)的 [1Mega x 16 Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器
文件页数/大小: 73 页 / 756 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM636165-XXI  
1M x 16 SDRAM  
4
Read and AutoPrecharge command  
(RAS# = "H", CAS# = "L", WE# = "H", A11 = V, A10 = "H", A0-A7 = Column Address)  
The Read and AutoPrecharge command automatically performs the precharge operation after  
the read operation. Once this command is given, any subsequent command cannot occur within a  
time delay of tRP(min.) + burst length . At full-page burst, only the read operation is performed in  
{
}
this command and the auto precharge function is ignored.  
5
Write command  
(RAS# = "H", CAS# = "L", WE# = "L", A11 = V, A10 = "L", A0-A7 = Column Address)  
The Write command is used to write a burst of data on consecutive clock cycles from an active  
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is  
issued. During write bursts, the first valid data-in element will be registered coincident with the Write  
command. Subsequent data elements will be registered on each successive positive clock edge  
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless  
another command is initiated. The burst length and burst sequence are determined by the mode  
register, which is already programmed. A full-page burst will continue until terminated (at the end of  
the page it will wrap to column 0 and continue).  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
NOP  
NOP  
NOP  
COMMAND  
NOP  
WRITE A  
NOP  
NOP  
NOP  
NOP  
DIN  
A
DIN A  
DIN  
A
DIN A  
3
don't care  
DQ0 - DQ3  
0
1
2
The first data element and the write  
Extra data is masked.  
are registered on the same clock edge.  
Burst Write Operation  
(Burst Length = 4, CAS# Latency = 1, 2, 3)  
A write burst without the auto precharge function may be interrupted by a subsequent Write,  
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt  
coming from Write command can occur on any clock cycle following the previous Write command  
(refer to the following figure).  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
NOP  
NOP  
NOP  
COMMAND  
NOP  
WRITE A  
WRITE B  
NOP  
NOP  
NOP  
1 Clk Interval  
DIN DIN B  
A
DIN B  
DIN B  
DIN B  
3
DQ's  
0
0
1
2
Write Interrupted by a Write  
(Burst Length = 4, CAS# Latency = 1, 2, 3)  
Preliminary  
9
Rev. 1.1 Apr. 2005  
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