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EM636165-XXI 参数 Datasheet PDF下载

EM636165-XXI图片预览
型号: EM636165-XXI
PDF下载: 下载PDF文件 查看货源
内容描述: 1Mega ×16同步DRAM (SDRAM)的 [1Mega x 16 Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器
文件页数/大小: 73 页 / 756 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM636165-XXI  
1M x 16 SDRAM  
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks  
earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto  
precharge function may be interrupted by a subsequent Read or Write command to the same bank  
or the other active bank before the end of the burst length. It may be interrupted by a  
BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read  
command can occur on any clock cycle following a previous Read command (refer to the following  
figure).  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
COMMAND  
READ A  
READ B  
DOUT A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
CAS# latency=1  
DOUT B  
DOUT B  
DOUT B  
DOUT B  
3
0
0
1
2
t
, DQ's  
CK1  
CAS# latency=2  
, DQ's  
DOUT A  
DOUT B  
DOUT B  
DOUT B  
2
DOUT B  
DOUT B  
0
0
1
3
t
CK2  
CAS# latency=3  
, DQ's  
DOUT A  
DOUT B  
DOUT B  
DOUT B  
3
0
0
1
2
t
CK3  
Read Interrupted by a Read  
(Burst Length = 4, CAS# Latency = 1, 2, 3)  
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt  
comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior  
to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O  
contention, a single cycle with high-impedance on the DQ pins must occur between the last read  
data and the Write command (refer to the following three figures). If the data output of the burst  
read occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at  
least one clock prior to the Write command to avoid internal bus contention.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
DQM  
COMMAND  
DQ's  
NOP  
READ A  
NOP  
NOP  
NOP  
NOP  
WRITE B  
DINB  
NOP  
NOP  
DOUT A  
0
DINB  
DINB  
2
0
1
Must be Hi-Z before  
the Write Command  
: "H" or "L"  
Read to Write Interval  
(Burst Length 4, CAS# Latency = 3)  
Preliminary  
7
Rev. 1.1 Apr. 2005  
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