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M52D32162A-7BG 参数 Datasheet PDF下载

M52D32162A-7BG图片预览
型号: M52D32162A-7BG
PDF下载: 下载PDF文件 查看货源
内容描述: 1米x 16Bit的X 2Banks手机同步DRAM [1M x 16Bit x 2Banks Mobile Synchronous DRAM]
分类和应用: 存储内存集成电路动态存储器手机
文件页数/大小: 32 页 / 808 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M52D32162A  
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)  
-7  
-10  
Parameter  
Symbol  
tCC  
Unit  
Note  
Min  
Max  
Min  
Max  
CAS Latency =3  
7
10  
-
9
15  
-
CLK cycle time  
1000  
1000  
ns  
1
CAS Latency =2  
CAS Latency =3  
CAS Latency =2  
6
9
8
CLK to valid  
output delay  
tSAC  
ns  
1
-
-
10  
Output data hold time  
CLK high pulse width  
CLK low pulse width  
Input setup time  
tOH  
tCH  
tCL  
ns  
ns  
ns  
ns  
ns  
ns  
2
3
3
3
3
2
2.0  
2.5  
2.5  
2.5  
1.5  
1
-
-
2.0  
2.5  
2.5  
2.5  
1.5  
1
-
-
-
-
tSS  
tSH  
tSLZ  
-
-
Input hold time  
-
-
CLK to output in Low-Z  
-
-
CAS Latency =3  
CAS Latency =2  
-
6
9
-
7
10  
CLK to output in  
Hi-Z  
tSHZ  
ns  
-
-
-
*All AC parameters are measured from half to half.  
Note: 1.Parameters depend on programmed CAS latency.  
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.  
3.Assumed input rise and fall time (tr & tf)=1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the  
parameter.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jul. 2009  
Revision : 1.6 6/32  
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