欢迎访问ic37.com |
会员登录 免费注册
发布采购

M52D32162A-7BG 参数 Datasheet PDF下载

M52D32162A-7BG图片预览
型号: M52D32162A-7BG
PDF下载: 下载PDF文件 查看货源
内容描述: 1米x 16Bit的X 2Banks手机同步DRAM [1M x 16Bit x 2Banks Mobile Synchronous DRAM]
分类和应用: 存储内存集成电路动态存储器手机
文件页数/大小: 32 页 / 808 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
 浏览型号M52D32162A-7BG的Datasheet PDF文件第1页浏览型号M52D32162A-7BG的Datasheet PDF文件第2页浏览型号M52D32162A-7BG的Datasheet PDF文件第3页浏览型号M52D32162A-7BG的Datasheet PDF文件第5页浏览型号M52D32162A-7BG的Datasheet PDF文件第6页浏览型号M52D32162A-7BG的Datasheet PDF文件第7页浏览型号M52D32162A-7BG的Datasheet PDF文件第8页浏览型号M52D32162A-7BG的Datasheet PDF文件第9页  
ESMT  
M52D32162A  
DC CHARACTERISTICS  
°C  
°C  
)
(Recommended operating condition unless otherwise noted, TA = 0  
~ 70  
Version  
Parameter  
Symbol  
Test Condition  
Unit Note  
-7  
-10  
Burst Length = 1  
tRC tRC (min), tCC tCC (min), IOL= 0mA  
Operating Current  
(One Bank Active)  
ICC1  
55  
35  
mA  
1
Precharge Standby  
Current in power-down  
mode  
ICC2P  
0.3  
0.2  
CKE VIL(max), tCC =15ns  
mA  
mA  
ICC2PS  
CKE VIL(max), CLK VIL(max), tCC =  
CKE VIH(min), CS VIH(min), tCC =15ns  
ICC2N  
3
1
mA  
mA  
Precharge Standby  
Current in non  
power-down mode  
Input signals are changed one time during 30ns  
CKE VIH(min), CLK VIL(max), tCC = ∞  
Input signals are stable  
ICC2NS  
ICC3P  
1.5  
1
CKE VIL(max), tCC =15ns  
Active Standby Current  
in power-down mode  
mA  
mA  
ICC3PS  
CKE VIL(max), CLK VIL(max), tCC = ∞  
CKE VIH(min), CS VIH(min), tCC=15ns  
Input signals are changed one time during 30ns  
10  
ICC3N  
Active Standby Current  
in non power-down  
mode  
CKE VIH(min), CS VIH(min), tCC=15ns  
Input signals are changed one time during 2clks  
All other pins VDD-0.2V or 0.2V  
ICC3NS  
2.5  
mA  
mA  
(One Bank Active)  
IOL= 0mA, Page Burst  
All Band Activated, tCCD = tCCD (min)  
Operating Current  
(Burst Mode)  
70  
40  
60  
40  
1
2
ICC4  
Refresh Current  
ICC5  
tRFC tRFC(min)  
mA  
°C  
TCSR range  
45  
70  
Self Refresh Current  
ICC6  
CKE 0.2V  
CKE 0.2V  
2 Banks  
1 Bank  
180  
160  
200  
180  
uA  
uA  
Deep Power Down  
Current  
ICC7  
10  
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).  
2.Refresh period is 64ms. Addresses are changed only one time during tCC(min).  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jul. 2009  
Revision : 1.6 4/32  
 复制成功!