ESMT
M52D32162A
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
BA
0
A11~A10/AP
RFU
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
W.B.L
TM
CAS Latency
Burst Length
Test Mode
CAS Latency
Burst Type
Burst Length
A8
0
A7
Type
A6
A5
0
A4
0
Latency
Reserved
Reserved
2
A3
Type
A2
0
A1
0
A0
0
BT = 0
BT = 1
0
1
0
1
Mode Register Set
Reserved
0
0
0
0
1
1
1
1
0
1
Sequential
Interleave
1
2
4
8
1
2
4
8
0
0
1
0
0
1
1
Reserved
1
0
0
1
0
1
Reserved
1
1
3
0
1
1
Write Burst Length
Length
0
0
Reserved
Reserved
Reserved
Reserved
1
0
0
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
A9
0
0
1
1
0
1
Burst
1
0
1
1
0
1
Single Bit
1
1
1
1
1
Full Page Length: 256
Note: 1. RFU (Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256 bit) is available only at sequential mode of burst type.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2009
Revision : 1.6 7/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
